| The system-on-a-chip (SOC) approach is a viable solution to meet the market demand for low-cost, high performance portable wireless systems such as mobile phones, pagers, and personal communication systems. To implement the mixed-signal SOC, the enabling technology should provide very good cross talk isolation between the clocking signals of the digital logic in the baseband and the very sensitive RF circuitry in the front-end. In addition, the technology should also provide high Q-factor on-chip inductors and high performance, low power active devices. This thesis demonstrates that SOI technology can be used to meet the requirements for RF SOC implementations. Initially, a SOI CMOS/LDMOS/BJT technology compatible with high performance passive components is proposed and developed. Also, a fully integrated RF power amplifier is implemented using this technology for the first time. Secondly, a TFSOI complementary BiCMOS technology is proposed and demonstrated with excellent cross-talk isolation, high-Q on chip inductors, and reduced self-heating. In this technology, a novel, high performance lateral BJT structure is implemented by taking advantage of the gate spacer to obtain a thin base width and a minimum base linkage to the external base for minimized base resistance. Also, p+ substrate contact rings are used for improved cross-talk isolation, appropriately doped TFSOI layer shields are used for high-Q inductor, and the source connected to the substrate is used to improve the self-heating. Thirdly, a novel 3D-BiCMOS technology is proposed and demonstrated. In this technology, the NMOS transistors are fabricated on the bulk substrate (bottom layer) and the PMOS transistors are fabricated on the single crystal top layer obtained using the selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE). In addition, the BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is similar to those fabricated on SOI, and the BJTs also have high performance. Finally, a novel Five-Channel (FC) NMOSFET using the SEG and LSPE is proposed and demonstrated. The FC-NMOS is an integration of a conventional bulk NMOS, two vertical NMOS, and a gate-all-around NMOS. The FC-NMOS has a 3.6 times higher current drive as compared to the conventional bulk NMOS. All of the above developed technologies will have great potential for use in RF SOC applications. |
