Multi-bit delta-sigma modulation technique for fractional-N frequency synthesizers

Fractional-N frequency synthesis provides agile switching in narrow channel spacing systems and alleviates phase-locked loop (PLL) design constraints for phase noise and reference spur. The inherent problem of the fractional-N frequency synthesizer is that the periodic operation of the dual-modulus divider produces spurious tones. Several techniques have been used to reduce spurious tones. Among those techniques, the delta-sigma modulation method provides arbitrarily fine frequency resolution and makes the spur-reduction scheme less sensitive to process and temperature variations since frequencies are synthesized by the digital modulation.; This thesis proposes a multi-bit Δ-Σ modulation technique as a spur reduction method to enhance the overall synthesizer performance, and the oversampling modulator performance is analyzed with the consideration of practical design aspects for frequency synthesizers. A prototype fractional- N frequency synthesizer using a 3-b third-order Δ-Σ modulator has been designed and implemented in 0.5-gm CMOS. Synthesizing 900 MHz with 1-Hz resolution, it exhibits an in-band phase noise of –92 dBc/Hz at 10-kHz offset with a reference spur of less than –95 dBc. Experimental results show that the proposed system is applicable to low-cost, low-power wireless applications and that it meets the requirements of most RF applications including multi-slot GSM, IS-54, CDMA, and PDC.