CMOS digitally programmable analog front-ends for third generation wireless applications

The wireless communication market has experienced rapid growth over the past few years. The introduction of digital data communication with digital signal processing created the base for the development of numerous wireless standards and applications. The demand for low power, low cost, universal wireless devices calls for the development of a single-chip third-generation (3G) receiver capable of adapting to the various communications standards in a low cost CMOS technology. The work presented in this thesis focuses on the realization of a digitally programmable baseband analog front ends for use in various integrated multi-standard 3G wireless receivers. In chapter 2 a baseband chain for a receiver designed to support both the GSM and DECT standards is developed. The chain offers a digitally controllable filter bandwidth, VGA gain setting as well as DC-offset compensation. Chapter 3 investigates the design of a CMOS low power baseband chain for an integrated Bluetooth receiver. The chain is designed using a new fully differential buffer circuit that can effectively implement filters with gain/filtering interleaved operations. Chapter 4 discusses modular 3G baseband building blocks with a focus on the design of a reconfigurable baseband chain structure. The circuits proposed retain flexibility and simplicity of design and are designed using the same active element. Using those circuits a baseband chain that can be digitally reconfigured is implemented. Finally, in chapter 5, the development of low power switched capacitor circuits is investigated. New techniques and OTA circuits for designing low power switched capacitor circuits are investigated.