Implementation considerations of algebraic switching fabrics

This thesis considers ASIC and physical issues in the implementation of a terabit/petabit switching fabric based on an architecture in algebraic switching theory [Li2000]. The objective is to optimize the cost effectiveness, feasibility, routing latency, and design flexibility. This switching architecture is 2-tier. It includes a main switching fabric, which is a self-routing non-buffering device and also an output switch built into every egress line interface for the performance of local switching. The building block of the main switching fabric is a concentrator , which is in turn constructed from 2 x 2 switching elements by self-routing control.; Two bit streams synchronously pipeline into the 2 x 2 switching element. The logic in the switching element uses the control bits at the beginning of the two bit streams to make the routing decision. The switching function is rather elaborate. It not only includes multicasting but also perform differential service by priority treatment. Therefore the number of control bits up front is rather large, especially when the number of ports on the switching fabric is large. It is only natural to expect the buffering of some bits, for example, by shift registers, when the 2 x 2 switching element is calculating the routing decision. The size of the bit buffer is deterministic to the hardware density, the latency, and the level of power consumption in ASIC implementation. It is important to minimize this buffer by proper encoding of the control signal and proper switching logic, since the 2 x 2 switching elements in the main switching fabric number by the thousands. Chapter 2 addresses this optimization problem, and the proposed solution reduces the size of the bit buffer to zero.; Chapter 3 generalizes the divide-and-conquer networks into a larger family that include networks of sizes in this continuous spectrum.; Chapter 4 proposes a new routing technique over a multistage packet switching network so that the protocol processing at inter-node line interface is almost eliminated. The proposed technique let cells cut through the multistage network without reassembling them into packets at the egress of every node. The technique saves almost all the cost in inter-node line cards.; In order to design a shared-buffer-memory switch that is as much in the self-routing style as possible, Chapter 5 presents the self-routing output switch (SROS) architecture with an embodiment for industrial implementation, wherein, a simple queuing strategy is presented. A distributed arbitration mechanism and related concurrent pre-configuring distributed arbitration (CPDA) algorithm are induced. (Abstract shortened by UMI.)...