Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGA

Millions of datacenters are operating all over the world, consuming up to 3% of the global electricity power and leaving a significant carbon footprint. Due to the uncertainty in the server load profile, most existing power-delivery designs are rated for the worst-case scenario, leading to significant design guard-bands, which results in unnecessary power losses and cost. This thesis addresses two areas that lead to inefficiency in datacenters: 1) unnecessary power losses in the central Uninterruptible Power Supply (UPS), and 2) conservative operation in Field-Programmable Gate Arrays (FPGAs).;The central UPS units in datacenters have a poor efficiency due to their back-to-back architecture, especially at light-load. A novel distributed UPS architecture and control scheme are proposed to provide granular local energy backup and increase the system efficiency. Lithium-Ion Capacitors (LIC) and a bi-directional dc-dc converter are used to provide short-term UPS functionality. A 200-kHz bi-directional multi-phase dc-dc converter operating in Hysteretic Current Mode Control (HCMC) is built to demonstrate the proposed scheme on a server, leading to a 33% reduction in average reactive power for one particular dynamic workload. Datacenter-level behavior is simulated, and the results show that the proposed architecture leads to 75% lower losses in the power delivering path compared to the datacenter with a central UPS.;FPGAs are most commonly operated at their nominal supply voltage, which in most applications is severely conservative. During compilation of the application-specific FPGA design, the Computer-Aided Design (CAD) tool determines the maximum achievable frequency of the user application. This analysis is based on the worst-case timing analysis of the critical path at a fixed nominal voltage, which usually results in significant voltage or frequency margin in a typical chip. Dynamic Voltage Scaling (DVS) has great potential to reduce the power in FPGAs; however, unlike in microprocessors, the critical-path delay of FPGAs is application-dependent, which creates unique challenges for the DVS of FPGAs. To address this issue, a robust universal DVS scheme for FPGAs is demonstrated which includes two phases: offline self-calibration and online DVS. The proposed DVS scheme is demonstrated on a 60-nm Intel Cyclone IV FPGA with a digitally-controlled dc-dc converter, leading to approximately 40% power savings in two typical applications.;Modern FPGAs operate with a core voltage of ∼1 V and can consume tens of Amps, and therefore load-dependent voltage fluctuations can lead to timing violations and logic errors. This is even more critical for DVS operation in FPGAs with limited voltage head-room. For reliable DVS operation of FPGAs, two schemes are presented: 1) automatic extraction of the DC resistance in the Power Delivery Network (PDN) for the resistive voltage drop (IR-drop) compensation, and 2) identification of the high-impedance frequency band(s) in the PDN to avoid large supply voltage ripple caused by the PDN resonance. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. Two fully synthesizable self-calibrated Analog-to-Digital Converters (ADCs) are used for core voltage sampling. The proposed schemes are demonstrated on a Cyclone IV FPGA board and real-time IR-drop compensation is shown to eliminate logic errors in an FIR filter application. It is also shown that by modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application is greatly extended.;The new techniques outlined in this thesis should lead to significant energy savings in future datacenters, which can help to increase their power density and reduce their carbon footprints.