Cost-effective programming for maximum power-efficiency of data centric applications on FPGAs

Datacenter workloads demand high throughput, low cost and power efficient solutions. In most of data centers the cost of operating datacenters dominates the infrastructure cost. Some solutions have been proposed and applied such as moving the data centers to cold geographical areas to reduce the cost of cooling them and virtualization of hardware resources to share the hardware with some software cost overhead. The ever growing amounts of data in the servers and the critical need for higher throughput, more energy efficient document classification solutions motivated us to investigate alternatives to the traditional homogenous CPU based implementation of document classification systems. Some heterogeneous systems are investigated where CPUs are combined with GPUs and FPGAs as system accelerators. GPUs take the advantage of SIMD parallelism and are able to run many threads in parallel. FPGAs as accelerators in a heterogeneous computing environment allow for the creation of flexible custom hardware solutions that can potentially offer increased power efficiency and performance gains. One of the main issues delaying wide spread adoption of FPGAs as standard heterogeneous system accelerators, in a similar manner to the way GPUs are used today, is the difficulty in programming them. Although there has been some reluctance to use high level programming of the FPGAs, it seems that HDL programming of FPGAs become cumbersome for nowadays need in data-centric applications and we need higher abstraction than what HDLs have offered to us. The OpenCL standard offers a unified C programming model for any device that adheres to its standards. An OpenCL FPGA based implementation of a document classification system is implemented and targeted different heterogeneous computing systems and find the best platform for different performance metrics such as cost of maintenance, portability, performance and performance per watt. In addition, the high level programmed FPGA results compared to those of obtained from the HDL programming of the FPGA to quantify the tradeoffs of moving to higher abstraction. Detailed cost analysis of high level synthesis (OpenCL) and low level synthesis (HDL) on FPGA are elaborated during the life cycle of classification system on a server. Tradeoffs of programming FPGAs as accelerators in heterogeneous computing environments using either high level parallel programming or low level parallel programming are discussed and explained.