Acquisition de donnees a haute resolution et faible latence dediee aux capteurs avioniques de position

The communication network and the detection mechanisms are two critical systems in a plane. Their performance has a direct impact on aircrafts. This is of particular interest for avionics designers, who have increasingly invested more and more in the development of these elements. As a part of a project in this domain, we introduce the design and the development of a smart interface for position sensors dedicated to flights (Smart Sensor Interface - SSI). This interface will serve to connect sensors of different technologies (electromagnetic, optical and MEMS) to the new communication network, AFDX. The role of this interface is to generate an appropriate excitation signal for certain types of sensors (R/LVDT), and to treat, demodulate, and digitize their output signals. The proposed interface is thus composed of a Signal Acquisition Path (SAP) and an Excitation Signal Generation (ESG). By adopting the Integrated Modular Avionics architecture (IMA), we can minimize the size of the classic interface, reduce its energy consumption and improve its reliability and its performance.;The focus of our design is particularly on the Data Acquisition Path (DAP). An Architecture characterized by a high resolution (14 bits) and a low latency (1.2 ms) of this module is introduced and developed in this prestigious work. This architecture was developed after a wellconducted study of existing solutions found in literature work and a detailed analysis of the problems arise in the design and implementation of this system (DAP). The conversion of the sensor signal into a digital signal is the most important step in acquiring data, as it sets the resolution of the acquired information and generates the majority of its latency. This module can also affect the reliability and stability of the system.;Among different models and architectures, the Delta-Sigma analog-to-digital converter (ADC) is preferred for this application (for better resolution). This converter is formed by an analog circuit (modulator) followed by digital filters. The complexity of the implementation, the processing delay and the output resolution are all susceptible to change depending on the architecture of these filters.;Thus, the main problem while designing such a system arises in the opposing evolution of the resolution and latency parameters; the improvement or evolution of one, results in the destruction of the other. Therefore, our work aims to provide one or more method to optimize the latency caused by the CAN while maintaining the same resolution of the desired data (14 bits). This optimization takes into account the objective of integrating the DAP in modules of small size and low power consumption. This proposed solution was implemented in order to validate the design of the conception of the interface. We are also interested to achieve the proposed solution and validate our design. The obtained results will be evaluated after following the manufacturing strategy.;The data acquisition unit is made up of two electronic components. The first component is an integrated circuit, which uses CMOS 0.13mum IBM technology and contains the analog part of CAN (SigmaDelta modulator). The second component is a Virtex-6 FPGA, which allows one to acquire the necessary digital processing required for the acquisition and conversion of the sensor signal. In the final version of the interface, our analog portion will be integrated with the analog portion of GSE in the same chip. The integrated digital logic in the (FPGA) role will thus provide digital data to the ESG module in order to generate the excitation signal.