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Design And Implementation Of Preprocessing Unit Of Ultra-short Baseline Positioning System Based On FPGA

Posted on:2021-06-29Degree:MasterType:Thesis
Country:ChinaCandidate:H ZhangFull Text:PDF
GTID:2480306047480784Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Ultra-short baseline underwater acoustic positioning is one of the current main methods of underwater navigation and positioning.It has the characteristics of high accuracy,small baseline size,and convenient use.The ultra-short baseline positioning system uses the time delay and phase difference of underwater acoustic signal propagation to measure the distance and direction of underwater targets to achieve tracking and positioning.In this paper,a preprocessing unit of an ultra-short baseline positioning system is designed,which performs multi-channel processing on the analog signals collected in real time,uses the correlation method for pulse compression,and estimates the delay according to the position of the relevant peak.According to the requirements and indicators of the ultra-short baseline positioning system,this article designs the positioning system pre-processing platform,using FPGA + DSP structure,with a high-performance EP2S90F780I4 N FPGA chip and three TMS320C6416 T DSP chips as the core,according to specific requirements.Expansion of peripheral circuits.The system realizes the collection of analog signals through an 8-channel high-speed analog-to-digital conversion chip ADS8568,and sends the results to the FPGA.On the FPGA platform,perform multi-channel preprocessing on the real-time collected signals,including digital filtering and sliding correlation processing,package the results of each part of the data,and send them to the two slave DSPs at any time through the EMIF bus for delay estimate.The core of this design is the SOPC system.In the SOPC system,the system work status control,data transmission,and data buffering are completed,and the work of each module is completed by interrupt triggering,which realizes the multi-channel multiplexing of FPGA.Write C language on the software platform to configure and control each module to realize system functions.Finally,the function of each part is verified by observing the signal waveform after power-on debugging.The output results of each part are compared with the calculation results in matlab to calculate the size of the error and analyze the cause of the error.In addition,the performance of the system has been analyzed and has reached the design requirements of the ultra-short baseline preprocessing unit.
Keywords/Search Tags:ultra-short baseline, FPGA, multi-channel preprocessing, SOPC system
PDF Full Text Request
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