A Low Noise Analog Front-End Circuit For EEG Acquisition System

Advances in electronics have opened up many new possibilities in health care for over six decades.Small and non-invasive devices with rich sensing,processing and communication capabilities have contributed to the development of wearable medical devices and various human activity monitors.With the development of sensors and wireless body area network(WBAN),wireless electroencephalogram(EEG)monitoring devices are widely used,of which the analog front-end(AFE)circuit for EEG acquisition system is one of the key parts.The accuracy of the signal acquired is determined by the performance of AFE.In order to satisfy the continuity and accuracy of the EEG monitoring system,a low-noise and low-power AFE circuit is quite significant.EEG,whose amplitude is extremely small,is the electrical activity of brain cells recorded on the surface of the skull's skin.The quality of the signal acquired can be seriously corrupted by various off-chip aggressors including DC offset from the electrodes and power-line interference(PLI)at 50 or 60 Hz,as well as on-chip aggressors such as DC offset,thermal noise,and flicker noise from the instrumentation amplifier(IA),which puts forward high requirements for the EEG acquisition AFE.This paper presents a low noise analog front-end circuit for EEG acquisition system,including a low noise instrumentation amplifier,a programmable gain amplifier(PGA)and a low-pass filter(LPF).Besides,an appropriate bandgap reference(BGR)is adopted to provide a common-mode bias voltage.This thesis discusses the characteristics of EEG signals and different types of biological electrodes,analyses common aggressors,explains the difficulties along with key techniques of EEG acquisition,and then deduces important specifications of the AFE circuit.In view of the low noise requirement,this thesis focuses on the design of the preamplifier.The low-noise amplifier is capacitively-coupled,to mitigate the effects of flicker noise and amplifier DC offset,the chopper modulation technique is employed.Meanwhile,to suppress the output ripple of the IA,a ripple reduction loop(RRL)is added.Unfortunately,chopper modulation will make the input capacitor unable to isolate the electrode DC offset any more.Therefore,a DC-servo loop(DSL)is needed,through which a quite low high-pass corner frequency could be obtained.Moreover,in case of common-mode interference as well as large signal attenuation caused by the voltage divider between electrode impedance and amplifier differential-mode input impedance,the precharge impedance-boosting technique is adopted.Additionally,a capacitive feedback PGA and a 2-nd order switched-capacitor LPF are implemented.The AFE designed is implemented in SMIC 0.18?m CMOS process.The simulation results show that the input impedance of the core low-noise amplifier is larger than 1.45G?,the power supply rejection ratio is 107d B,the common-mode rejection ratio is 98d B,and the input-referred noise in 0.1Hz-100Hz pass band is only 0.7?V_rms from a 1.2V supply and 0.6V common-mode reference voltage.The PGA realizes a variable gain from 16d B to 46d B with10d B step,and the-3d B cut-off frequency of the LPF is about 250Hz.The requirements of the AFE circuit could be well satisfied.