Research And Design Of High-Efficiency Low Dropout Linear Regulator In MEMS Geophone

The geophone based on micro electro mechanical system(MEMS)has the advantages of large dynamic range,high precision and small volume,so it has a broad application prospect in seismic data acquisition.The MEMS geophone contains a noise sensitive analog module,which needs a low dropout linear regulator(LDO)with low noise and low ripple to provide a stable working voltage.The MEMS geophones are often powered by batteries.In order to extend the working time,low power LDO must be used.However,directly reducing the static current of the LDO will lead to its performance degradation,so it is necessary to improve the current utilization to ensure the performance under low static current conditions.This thesis has made an in-depth study on how to improve the overall efficiency of LDO,combined with the current development trend of LDOs,two high-efficiency LDOs applied to MEMS geophones are designed.The first chip is a high efficiency LDO with low impedance transient current enhanced buffer.In order to ensure the stability of the system and improve the transient response,a low impedance transient current enhanced buffer is proposed.The novel voltage buffer can reduce the output resistance without dissipating large quiescent current,thereby pushing the pole at the gate of the power transistor to a very high frequency.At the same time,this buffer can also increase the slew rate of the output stage,thereby improving the transient response.In this design,Miller compensation of series zero resistance is used as compensation network,and the stability of LDO under full load is analyzed by calculating small signal transfer function under different load.The LDO has been fabricated using SMIC 0.18μm CMOS process.Its working voltage range is 1.8-2.2V,output voltage is 1.6V,maximum load current is 200 m A,quiescent current consumption is about 48μA,and maximum current efficiency can reach 99.976%.The measured results show that,under the condition of 1μF load capacitor,the output voltage changes 76 m V when load step changes of 200 m A/100 ns.The second chip is a wide input range transient enhanced high efficency current feedback LDO.This design uses current feedback to reduce the lowest working voltage of LDO.In order to improve the transient response under the condition of keeping low quiescent current,a dynamic controllable reference current source is proposed in this thesis.In addition,an enhanced active resistance network is used to replace the MOS transistor connected with diodes in the traditional current mirror to form a nonlinear current mirror.The combination of the above two structures not only improve the slew rate of the output stage,but also increase the loop bandwidth.The LDO has also been fabricated using SMIC 0.18μm CMOS process.Its working voltage range is 0.8-2.2V,output voltage is 0.64 V,maximum load current is 50 m A,quiescent current consumption is about26μA,and maximum current efficiency can reach 99.948%.The measured results show that,under the load condition of 100 p F,when load step changes of 50 m A/300 ns,the overshoot voltage is117.5m V and the undershoot voltage is 167.5m V.Compared with the previous work,the two LDO chips proposed in this thesis have high comprehensive efficiency,which proves that the novel structure proposed in this thesis can effectively improve the current utilization.