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Research And Implementation Of Timing System Based On IRIG-B Code

Posted on:2019-10-13Degree:MasterType:Thesis
Country:ChinaCandidate:B LvFull Text:PDF
GTID:2480306470994239Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In the modern society,defense military,communications and electronics,power and application engineering,and basic science research,etc.,demand for precise time services is constantly increasing and demand is increasing.In the past,time services were basically provided by quartz clocks and could no longer satisfy the high-level requirements for time accuracy at this stage.Therefore,for some specific users and specific needs,it is necessary to design a timing system that is compatible with it.This paper designs and implements a set of precise,easy-to-operate,and feature-rich timing system for defense and naval applications.This design aims to provide a timing system based on FPGA technology using the GPS and BDS signals as the reference source.The system requires the completion of local time,1pps signal,IRIG-B(DC)code,IRIG-B(AC)code,5MHz and 10 MHz sinusoidal carrier output.This design is mainly divided into two parts,the hardware design part and the embedded software design part.The hardware design implementation part takes the FPGA chip as the core,and designs and implement other functional modules and peripheral circuits.The entire hardware implementation part is divided into four modules to be designed respectively: a time receiving module,a data processing module,a B code generating module and a carrier generating module,which are composed of eight functional board cards.Each functional board uses the same model FPGA chip as the core,and integrates different functional modules and peripheral function circuits according to requirements,which together form the hardware part of the timing system.The embedded software design part also takes FPGA as the core,and carries out embedded software programming based on each function board card.This part is divided into three modules according to the function: time extraction module,time integration module,and B code conversion module.The embedded software design part realizes the conversion of the initial time information received by the external antenna to the IRIG-B code.After system feasibility verification,the timing system designed in this paper overcomes the shortcomings of the previous timing system,which is low cost,easy to carry,high accuracy and easy to debug,and can meet the application in many fields.
Keywords/Search Tags:GPS, BeiDou, IRIG-B code, FPGA
PDF Full Text Request
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