A Software/hardware Co-design For Energy Efficient Graph Processing On FPGA Platform

Graph structure is widely used in various fields due to its expression efficiency.Nowadays,the scale of graph data has grown exponentially,and it's important to complete graph data processing efficiently.However,existing general-purpose processor architecture is difficult to solve the irregular problems in graph computing,which makes graph computing accelerators gradually become the mainstream of research.Existing graph computing accelerator adopt vertex-centric programming model to make full use of the parallelism between vertices,and use a bitmap structure to maintain a set of active vertices at runtime.We find that the bitmap-based storage mode will cause serious additional overhead when the number of active vertices is small,resulting in the limited graph computing performance.Based on the above findings,we propose a software/hardware co-design for graph processing.The system dynamically selects the appropriate storage model,and adopts optimization methods such as point data caching and edge data prefetching to improve memory access efficiency.First,we propose a Push-Pull programming model based on bitmap and queue,which allows the selection of the appropriate active vertices storage structure during graph processing.Second,we design an accelerator architecture to ensure efficient management of storage structures.In addition,we use FPGA on-chip resources to realize the connection between the computing units,thereby eliminating the time loss of the computing pipeline.And we adopt the optimized design of vertex data access to reduce the random access of vertex at runtime.And we also design a dedicated on-chip structure to support edge prefetching,thereby changing random edge access into sequential edge access.Experiments show that compared to the FPGA-based graph computing system ForeGraph,our system can achieve 1.36×?3.02× speedup.And our optimizations greatly ensure system performance.