Research And Implementation Of High-bandwidth And Low-power SRAM In Coherent Integration Of GPS Capture Engine

With the rapid development of wearable devices and Io T,the demand for low-power GNSS modules has grown a lot.The work of the capture engine causes the most of the power consumption of the GNSS module by frequent access to static random access memory(SRAM)during the coherent integration process,while the SRAM generated by commercial compilers compromises the energy efficiency of the entire system due to its traditional design.Applied in the coherent integration scenario in the GPS capture engine,the high bandwidth requirement for memory during the coherent integration is met,and the energy efficiency of the access to SRAM is improved.In terms of the "write-in-situ after reading" feature,an optimized discharge mode is proposed.By comparing the read data and write-back data,the same data is not written back,thus the bit line discharge mode is optimized.In order to reduce the ineffective power consumption caused by the half-select issue,a sharing sense amplifier for reading and writing is proposed,which uses multiple beats in the read cycle to complete the "shift peak read" operation of the four columns of data,and uses a single sense amplifier to complete the "simultaneously write" operation of the four columns of data in the write-back cycle.This design both ensures a low level of peak current and meets the demand for high data-bandwidth.A high-bandwidth,low-power SRAM,with a capacity of 256×128bits,is proposed based on TSMC 28 nm process in a fully customized flow.The results of the post simulation show that,compared with the same capacity SRAM generated by the traditional commercial compiler,the power consumption is reduced by 78.9% at 0.7V,the bandwidth is expanded by 4 times.