Research On The Compact Model And Memory Cell Circuit Of FeFETs

In the era of big data,data storage has grown rapidly,and there is an urgent need for higher performance storage.In the horizontal comparison of the existing new non-volatile memory,ferroelectric memory（FeRAM）shows the advantages of low power consumption and high writing speed,but the early ferroelectric materials are incompatible with CMOS process,large in size,and destructive readout.The research on storage devices（such as FeRAM）based on the mechanism of ferroelectric polarization has stagnated.This dilemma was not broken until the discovery of good ferroelectricity in doped HfO₂ materials.Thanks to the advantages of HfO₂ material’s good scalability and compatibility with CMOS technology,the research of Hf-based ferroelectric memory devices has once again attracted attention,and FeFET with 1T structure has become an ideal type of memory due to its non-destructive readout method.In order to provide a theoretical basis for the current ferroelectric material preparation and FeFET circuit design,a compact model that can accurately simulate the FeFET storage mechanism is needed and used in the design of read and write circuits.Based on the polarization P-E hysteresis curve of HfO₂ ferroelectric material and Preisach-Model,this paper uses HSPICE software compatible with circuit simulation to model the ferroelectric layer.The correctness of the ferroelectric layer model is accurately verified through the hysteresis P-V curve and the I-V and C-V curves.The FeFET model is obtained by coupling the ferroelectric layer model and the MOSFET.And a memory cell circuit is proposed,and the simulation obtains good read and write performance.Specific research results include:calibration with the P-V curve of Hf_0.5Zr_0.5O₂ prepared in the laboratory,the simulated saturated polarization P_s is 23.35μc/cm²,the residual polarization P_ris 6.25μc/cm²,and the coercive voltage V_c It is 0.85V.Compared with the experimental data,the fitting error is within 5%,which proves that the ferroelectric layer model made in this paper is practical.Then use the HSPICE ferroelectric layer model to couple with the CMOS compatible130nm N-MOSFET model in BSIM4 to obtain the FeFET model.The performance verification of the FeFET model shows that after writing"0"/"1"to the FeFET,the two I-V curves show a memory window（Memory Window,MW）.The simulation results show that MW is negatively correlated with the dielectric constantε_FE of the ferroelectric layer and positively correlated with the chargeΔQ_FE present in the gate plate of the MOSFET after programming.Finally,a circuit model of the FeFET memory cell is proposed.We use a CMOS transmission gate to select its location.After programming the memory cell with a non-negative voltage writing scheme,the"0"/"1"information stored in the FeFET can be obtained through the reference voltage and read/write time is less than 100ns.The simulation results show that our FeFET model can well implement its read and write functions in FeFET circuits.