Design And Verification Of 1GHz Radiation Hardened PLL Circuit In 28nm Process

With the development of aerospace industry,PLL,as one of the core devices of spacecraft,has higher requirements for its performance and reliability.With the development of IC process nodes,the influence of irradiation on PLL becomes more and more serious.Charge pump PLL has been widely studied and applied because of its wide acquisition range and small locking phase error.Based on the basic principle of charge pump PLL,according to the forward design methodology of IC,this paper designs an anti irradiation PLL with low phase noise and small area cost.The main research work and achievements are as follows:First,according to the requirement of low phase noise,the method of adding delay chain is studied to eliminate the dead zone of the PFD and reduce the crosstalk introduced by the reference signal so as to reduce the phase noise;on the other hand,the output signal of the low-pass filter is directly used to power the VCO,and the oscillation frequency of the VCO is controlled through the change of the signal,reduce the interference of power and substrate noise to VCO,so as to reduce the overall phase noise.The chip test results show that the phase noise of VCO is about-90 d Bc/Hz at 1MHz.Second,in view of the requirement of small area cost,because the filter capacitance and power decoupling capacitance occupy a large area,there are no other signal lines except the power ground wire on the two parts of the layout.The power grid is generally paved with high-level metal,so in this case,the middle metal layer can be used to build a special shape,making full use of the middle metal layer capacitance.To a certain extent,reduce the layout area.The core area is 0.06mm~2.Thirdly,in order to meet the requirements of anti radiation,double exponential current source is used to simulate the radiation effect and determine the sensitive nodes of the circuit.The lock-in detection signal is introduced into the charge pump module.When the PLL loses its lock under the radiation condition,it will open more charge pump units,increases the loop bandwidth,shortens the frequency acquisition time,accelerates the lock-in of the PLL,that is,reduces the influence time of radiation effect on the circuit.In addition,the radiation resistance of the digital module is improved by strengthening the circuit and layout of the standard logic.Especially,for the flip-flop of the PFD the anti-SEU and anti-SET are carried out to further improve the anti radiation performance of the PLL.By comparing the simulation results before and after the reinforcement,the effectiveness of the reinforcement scheme is verified.Fourthly,28nm process is used to tapeout the design.The measured results of the chip show that the maximum minimum period and the ideal period deviation are no more than100ps,and the mean square error is 15.3ps.The phase noise of the chip is-108d Bc/Hz at1MHz.The reliability and rationality of the circuit simulation are verified by comparing the measured data with the simulation data,and the reasonable suggestions for the next work improvement are put forward.