Study Of Readout Control Based On MAPS Silicon Pixel Detector System

The Beijing Electron Electron Collider Ⅱ(BEPC Ⅱ)is a large-scale collider used to study tau-char physics,and has made an indelible contribution to the development of high-energy physics experiments in our country.Beijing SpectrometerⅢ(BES Ⅲ)is a high-precision universal detector system matched with BEPC Ⅱ.The main drift chamber(MDC)is the particle track detector of BESⅢ.Due to the longterm high background environment,the internal track chamber of the MDC has experienced aging problems,and its performance has dropped sharply.In order to avoid the risk of failure of the inner drift chamber,a R&D scheme for the upgrade of the inner drift chamber based on Monolithic Active Pixel Sensor(MAPS)was proposed.The scheme plans to use the MIMOSA28 chip to build a 1/10-scale silicon pixel detector prototype.The study of electronics matching the detector is a very important part of the whole detector research process,wherein the study of FPGA firmware for the readout control of detector module data is indispensable.At present,the hardware part of the detector module and the matching data readout system have been initially developed.It is also necessary to study the readout control of the MAPS detector system on the basis of the existing hardware,so as to realize the continuous readout of the detector module data and the alignment of the even between the modules,and improve the data efficiency.According to the data characteristics of the MIMOSA28 chip,this thesis studies the readout control of the detector system based the MIMOSA28 chip,including the construction and realization of the readout firmware function module,the simulation of the readout firmware and the experimental verification.First,this thesis creats a FPGA data readout firmware based on the characteristics of the data of MIMOSA28 chip,which contains three main functional modules,namely the FPGA configuration and working status control of the MIMOSA28 chip,continuous data readout and processing with trigger marks,and high-speed data transmission.Next,a test file was written,and the simulation test of some functional modules and the overall test of multiple modules were carried out on the ISim software.The simulation results show that the functional modules are working properly,the FPGA firmware program can correctly process and output the data of continuously readout,and the output data format meets expectations.Finally,a laboratory test system was built to further test and verify the FPGA firmware,which includes five layers detector modules,readout electronics,data acquisition system,signal generator,power supply module and so on.Laboratory tests have found and solved the problem of unsynchronized working clocks when the multiple detector modules fetch data together.Through the analysis of the test results,the correctness of the continuous readout method with trigger mark was verified.It is concluded that taking the data of the previous frame,the current frame and the next frame of the valid trigger number,a total of 3 frames of data for data analysis will not cause data loss.The radioactive source response and imaging performance of the detector module have been study and tested through the laboratory test system.The test results show that the functions and the performance of the new FPGA firmware meet the expected goals.At the same time,it verifies that the method of selecting 3 frames of data for analysis is correct.