Research On Optimization Of Electric Field In Terminal Area Of Press-pack IGBT Chip

With the increasing development of power systems,the advantages of DC transmission have become increasingly prominent.HVDC circuit breakers can quickly isolate faults and prevent the development of short-circuit current through rapid action,which has become a key technology to ensure the stable operation of DC power grids.Because of the advantages of double-sided heat dissipation,higher power density,and higher reliability,Press-pack IGBT devices are highly suitable for use in HVDC circuit breakers.However,the electric field at the edge terminal area of an IGBT chip is relatively high,partial discharge at the rim of the metal parts on the surface or flashover along the surface of the terminal area is likely to occur,which leads to early dielectric breakdown,affecting the reliability of the IGBT device.Therefore,it is necessary to optimize the electric field at the terminal area to increase the breakdown voltage of the chip,which is of great significance to improve the reliability of the IGBT device.An optimization design method of the field limiting rings(FLRs)was studied in this paper.The parameters of the FLRs at the terminal area under steady state and transient state are optimized to obtain a uniformly distributed electric field,and the accuracy of the optimization is verified by Silvaco TCAD simulation.Firstly,taking an actual 3300V/50A Press-pack IGBT chip as a case study,the electric field optimization problems at the edges and corners of the terminal area under the DC stress are studied.A steady-state equivalent resistance circuit model of the terminal area is proposed.The relation of the resistance parameters in the model is fitted through Silvaco TCAD simulation.The circuit equations are established and the fitting relationship is brought into the equations,and then the optimization model is obtained.Combined with a particle swarm optimization algorithm(PSO)to optimize the parameters and layout of the FLRs,and the accuracy of the optimization method is verified by the Silvaco TCAD simulation model.Then,the electric field optimization problem at the edge of the terminal area at high frequency is studied,and the electric field distribution at 10kHz is analyzed.A high frequency equivalent capacitance circuit model of the terminal area is proposed.Combined with PSO,the parameters and layout of the FLRs are optimized.Finally,based on the simplified transient conditions,the change rule of the optimal solution and the maximum breakdown voltage(Vb)at different frequencies are summarized,which provides a reference for selecting the optimal ring spacing s under transient conditions.The conclusions obtained are as follows:First,as the frequency increases,the value of the ring spacing gradually increases.Second,as the frequency increases,the maximum breakdown voltage(Vb)shows a downward trend.