Research On Energy Saving Scheme And Key Technology Of Real-time OFDM-PON System

With the rapid development of multimedia services such as ultra-high-definition video,webcasting,and mass data transmission,and the rise of the 5th generation mobile networks(5G)services,the demand for Ethernet bandwidth has increased sharply.Orthogonal Frequency Division Multiplexing(OFDM)technology has become one of the candidate technologies for the next generation of passive optical networks(PON)due to its high spectrum utilization,strong anti-dispersion capabilities,and flexible bandwidth allocation.Since the modulation/demodulation technology in the OFDMPON system is accompanied by complex digital signal processing(DSP),compared to other PON systems,OFDM-PON usually consumes more energy.To promote the construction of green optical networks and the practical application of OFDM-PON,this thesis is dedicated to the study the issues of energy-saving of real-time OFDMPON systems.Considering the broadcast characteristics of the downlink of the PON system,in the third chapter of this thesis,an energy-saving scheme which is based on clock-gating technology and applicable for real-time OFDM-PON systems is proposed.The energysaving receiver realizes the selective processing of the received data frames by recognizing these data frames at the physical layer and uniformly controlling the operating clock of the DSP module through the clock-gating module to avoid the waste of power consumption of the processing in non-local frames.Clock-gating module consists of only one BUFGCE,which has extremely low hardware implementation complexity.The energy-saving scheme introduces pipeline processing technology and designs a frame alignment module to fix the data processing delay,thereby reducing the complexity of system hardware implementation and achieving precise control of delay turn-off of the operating clock of DSP module.Furthermore,this thesis mathematically models the chip power consumption and energy-saving efficiency for the clock-gating based energy-saving scheme by analyzing the influencing factors of chip power consumption.Experiments are undertaken in the Xilinx ML605 field programmable gate array(FPGA)based real-time intensity modulation direct detection(IMDD)OFDM-PON platform,the results prove the correctness of the proposed models and also show that 51% power consumption of FPGA chip can be saved compared with conventional scheme,and the degradation of transceiver performance induced by clockgating technology is negligible.In the real-time OFDM receiver used in the above research,the signal processing parallelism is 32,the number of fast fourier transform(FFT)points is 64,and the FFT module adopts the open source Spiral structure.The power measurement results show that the FFT module in the receiver based on the Spiral structure occupies more than50% of the dynamic power consumption of the baseband signal processing module.To further reduce the receiver’s chip power consumption,combined with the system characteristics,the fourth chapter of this thesis designs a low-power FFT structure named Half-parallel,which use 32-point FFT to complete 64-point FFT calculation.The proposed Half-parallel structure is mainly composed of a 32-point FFT module and a butterfly operation module.In order to meet the requirements of system throughput,Half-parallel adopts a full pipeline design,in which 32-point FFT is a full parallel pipeline structure.Therefore,the intermediate stage calculation results of Half-parallel FFT can be directly input to the next stage of the pipeline for calculation,without openning an additional storage area to cache the data stream.In order to verify the correctness and energy-saving efficiency of Half-parallel FFT,simulation is undertaken on the OFDM-PON platform.The numerical simulation results show that Half-parallel fixed-point FFT has a calculation accuracy close to MATLAB floating-point FFT and Spiral fixed-point FFT where the word length of fixed-point FFT is set to 16.Power simulation results show that the Half-parallel structure can successfully reduce the dynamic power consumption of the FFT module by 90% compared with the Spiral structure,and the dynamic power consumption of the FFT module is reduced from 57%of the total dynamic power consumption of the baseband signal processing module to12%,which indicates that the FFT module is no longer the main source of dynamic power consumption for the baseband signal processing module.Finally,the Halfparallel FFT is applied to the real-time OFDM receiver,and the experimental results show that it has high applicability on the real-time platform and can effectively reduce the receiver’s chip power,which is helpful in accelerating the construction of energysaving OFDM-PON systems.