Task Scheduling Of Multi-core And Multi Partition Operating System Based On ARINC 653

In recent years,the continuous breakthrough of avionics technology has led to the rapid development of aviation industry,Integrated Modular Avionics(IMA)system is gradually replacing the traditional distributed federal avionics system and becoming the mainstream system architecture in this field.Compared with the traditional distributed federal avionics system,the avionics system based on IMA architecture has the advantages of high reliability,high integration,low power consumption,light weight,easy maintenance and so on.ARINC 653 was proposed in 1997 as a real-time operating system(OS)specification.It not only defines the behavior logic of specification of realtime OS under IMA architecture,but also provides standard API interface specification for airborne applications.ARINC 653 initially designated a single core processor as the hardware platform,and there is a mature two-level scheduling model on the single core processor platform.However,in recent years,the rapid development of avionics systems has brought about an increase in the scale of airborne missions and processing requirements,the single core processor platform has been overloaded,and cannot continue to meet the real-time scheduling requirements of ARINC 653 standard multi partition OS.It is an inevitable trend that the multi-core processor platform will naturally widely used in the field of avionics systems.Compared with the mature two-layer task scheduling model of the ARINC 653 standard multi partition OS on a single-core processor platform,its scheduling model on a multi-core processor platform has not formed a unified international standard,there are many uncertainties.In this paper,a BMPRR scheduling algorithm is proposed to address the problem of relatively large idle time and low processor average utilization in ARINC 653 multi partition OS on multi-core processor platform.The main work and research results are as follows:1.This paper analyzes the mature two-level scheduling model of ARINC 653 standard multi partition OS on single core processor platform.Aiming at the problem of low average utilization of processing cores in ARINC 653 standard multi partition OS for task scheduling in a multi-core processor environment,a BMPRR scheduling algorithm is proposed in this paper,which includes the task model,task scheduling model,the constraints of task scheduling and the selection of task scheduling parameter and so on.Data reasoning simulation results show that the BMPRR scheduling algorithm can significantly improve the average utilization of multi-core processors while ensuring the strong real-time requirements of avionics system task scheduling.2.A partition-processor mapping strategy is given.This strategy draws on the task allocation methods in traditional multi-core processor task scheduling architectures such as AMP,SMP,BMP,etc.It realizes the partition-processor binding in the microkernel virtual machine manager of the system at a ratio of 9)∶ 1(9)≥ 1),and each processing core generates an independent scheduling domain based on the result of the partition-processor binding.Experimental results show that this partitionprocessor mapping strategy cannot only significantly reduce the number of partition splits,ensure the relative integrity and independence of partitions,but also improve the certainty of task scheduling.3.Data reasoning simulation experiments are carried out,Compare and analyze the feasibility and superiority of the BMPRR scheduling algorithm from three performance indicators: the real-time schedulability of the algorithm,the delay characteristics of the task,and the average utilization of the multi-core processor.This paper uses the instantiated avionics system task set S2 to perform data reasoning simulate.The data reasoning simulation results show that the BMPRR scheduling algorithm can significantly improve the average utilization of multi-core processors on the premise that the avionics system task set can be scheduled in real time,but it cannot guarantee the task delay.The characteristics reach the optimal value.All the research work carried out in this article has been supported and funded by a certain research institute of China Electronics Technology Group Corporation.The conclusions and achievements of the research work in this article pave the way for the development of a certain type of carrier based fighter.