| With the rapid development of information technology and semiconductor technology,the market demand and application scale of data centers are increasing,and its huge energy consumption has gradually become a serious problem that cannot be ignored.The power supply voltage required by various equipment in the data center is different,and the power supply voltage required by the CPU and other loads is even lower than 1V.It’s difficult for traditional Buck converter to convert 48 V input voltage to 1V output voltage since it cannot meet the requirement for generating narrow pulse control signal required by the high conversion ratio and efficiency.Therefore,the thesis designs a DC-DC converter with high conversion ratio and high conversion efficiency.Aiming at addressing the problems existing in traditional Buck converters when used in step-down applications asked for high conversion ratio,the thesis makes innovative research on the topology and control method of the converter,which greatly improves the conversion efficiency of high conversion ratio converter.Firstly,a hybrid topology of Full-Bridge Double Step-Down（FB-DSD）suitable for high conversion ratio step-down application is proposed for the first time in this thesis.In the FB-DSD converter,the transformer is used to realize the voltage transformation,which can increase the duty cycle of the control signal of the power MOS,and effectively solve the problem of narrow pulse width of the control signal in the application of high convertion ratio.The voltage stress of power MOS can be reduced by using the flying capacitor with half of the input voltage drop and voltage stress can be therefore released,so that the power MOS with lower withstand voltage can be used to reduce switching loss and conduction loss.In addition,the flying capacitor can also act as a DC-blocking capacitor,which can prevent the transformer from magnetic bias and ensure the reliable operation of the converter.Secondly,a soft switching control method for FB-DSD converter is proposed in this thesis,which uses the resonance of the parasitic capacitance of the power MOS and the leakage inductance of the transformer,and then combines timing control to achieve the zero-voltage turn-on or low-voltage turn-on of the power MOS.Since the FB-DSD converter reduces the voltage at the switching node of the circuit,it is easier to achieve zero-voltage turn-on with resonance.Compared with LLC and other resonant converters,the FB-DSD converter proposed in this thesis can keep the switching frequency invariable and is beneficial to optimize the EMI characteristics of the system.Finally,based on the 0.18μm BCD process,a valley current mode Constant On-Time（COT）control chip is designed for FB-DSD topology.The two-phase control signal adopts the control mode of fixed 1/2 switching cycle delay,and this control method is used to prevent the two-phase control signals from overlapping.At typical application（the input voltage is 48 V,the output voltage is 1V,and the switching frequency is 500 k Hz）,the peak efficiency of FB-DSD converter controlled by valley current mode COT is94.84%,which is far higher than the reported results.The topology and control method of high conversion ratio step-down converter researched in the thesis can effectively improve the conversion efficiency,keep the switching frequency constant,and address the technical challenges in the application of high input voltage,high conversion ratio and large output current. |
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