Design And Implementation Of UAV Detection Radar Signal Processing System

In recent years,due to the frequent safety accidents caused by illegal flight of Unmanned Aerial Vehicle(UAV),the effective monitoring of UAV has become an urgent problem.Radar is the first choice of UAV detection method because of its advantages of all-weather,wide coverage,long range and high detection accuracy.According to the design index of radar signal processing system,this paper carried out the design of algorithm scheme,hardware scheme and hardware,the work mainly includes the following three aspects:(1)According to the system design index,a complete algorithm flow including digital down conversion,pulse compression,moving target detection and constant false alarm rate detection is designed;combined with the system requirements,the hardware scheme is designed,and the core devices such as direct digital synthesizer,Analog-to-Digital Converter(ADC)and Field Programmable Gate Array(FPGA)are selected.(2)According to the function,the hardware of the system is divided into seven modules,which are transmitting signal generating module,ADC sampling module,memory module,control and communication module,FPGA module,clock management module and power management module.The schematic design and Printed Circuit Board(PCB)design are carried out.(3)Build debugging environment to debug the system,and verify that the system hardware works normally and the algorithm flow is feasible.After the completion of the system debugging,the whole radar is debugged.The test results show that the UAV detection radar works well and meets the requirements of the system design.According to the characteristics of low altitude,slow speed and small UAV,the radar adopts narrow beam and high speed resolution technology to improve the detection ability of UAV target.In terms of hardware,the system adopts Quad Data Rate SRAM(QDR SRAM)is used for data storage,which can simplify the system design while obtaining the maximum memory bandwidth;The clock management module uses the zero delay mode of the phaselocked loop to generate the system clock,the input clock and the output clock have a fixed phase,which improves the stability of the system timing.