Research And Verification Of The Backside Heat Dissipation Structure Of High-power Chips

As the integration of power chips becomes higher and higher,the feature size of the chip is reduced while also bringing about extremely severe thermal reliability problems.In order to make the chip work normally and improve the service life of the chip,it is particularly important to study the thermal characteristics of high-power chips and to design a reasonable thermal conduction structure.This dissertation takes the heat dissipation characteristics of high-power chips as the research object,and carries out the theoretical model and simulation verification of the heat dissipation structure with cylindrical heat dissipation through silicon vias embedded on the back of the power chip and quadrangular trellis heat dissipation through silicon via arrays.Theoretical research mainly includes the thermal resistance reduction mechanism and the steady-state thermal resistance model of the heat dissipation structure.The simulation verification mainly includes the thermal resistance simulation of the heat dissipation structure and the research and verification of the thermoelectric coupling phenomenon of the chip substrate.The specific work mainly includes the following points:1.The heat dissipation design scheme and the heat dissipation mechanism to reduce the thermal resistance of the chip are proposed,and the comparison of the theoretical thermal resistance of the chip under the heat dissipation structure of the heat dissipation silicon via array and the thermal resistance after the chip is thinned is studied.The steady-state thermal resistance models of cylindrical holes and quadrangular mesa holes are proposed,and their accuracy is verified by finite element software simulation,which can provide guidance for the thermal design of high-power chips.2.The influence of the related parameters of the heat dissipation TSV array on the thermal resistance of the chip is studied,and the thermal resistance of the heat dissipation TSV array with different structures and different parameters and the thinned chip thermal resistance are compared and analyzed,and the aperture of the heat dissipation TSV array is optimized.,Hole depth,hole spacing and other related parameters.3.Considering the parasitic resistance of the silicon substrate,when current flows,the silicon substrate itself will also generate heat.The thermoelectric coupling characteristics of the cylindrical heat-dissipating through-silicon via array and the quadrangular trellis-shaped heatdissipating through-silicon via array embedded in the silicon substrate with different doping concentrations are studied.Based on the substrate-related parameters in a mature integrated circuit process,a specific heat dissipation through silicon via array was designed,and the thermoelectric coupling characteristics of the embedded heat dissipation through silicon via array in the silicon substrate and the chip thinning were compared and verified.The correctness of the designed heat dissipation structure and related theoretical models.