Verification Of BOOM Processor Based On RISC-V Instruction Set

In recent years,the RISC-V instruction set has gained close attention worldwide and a large number of companies have joined.Various well-known enterprises and universities have designed their own RISC-V processors,such as the BOOM(Berkeley Out-of-Order Machine)of Berkeley University,and Xuan Tie 910 of the T-head.However,as a new reduced instruction set,the verification of the RISC-V instruction set processor is faced with the problems of fewer test sets,inaccurate dual-core reference models,and chaotic dual-core consistency verification methods.In this paper,the BOOM modified by the internship unit is taken as the research object,and the three aspects of function points,test incentives and discrimination methods are studied and explored,and a verification scheme is constructed to complete the verification.Firstly,the functional model research was carried out,the literature and design code were read,various functional points were set,and the functional model was built.Secondly,research on incentive generation was carried out.This paper analyzes the shortcomings of the original verification function coverage and real program requirements,formulates a constrained randomization generation strategy,implements six functional scenarios,and builds a random instruction generation platform.The random instruction generated by the random instruction generation platform and the directional test are combined to complete the test incentive generation work.Finally,a verification method study was carried out,and a verification scheme based on a reference model comparison system was developed,supplemented by a floating-point verification sub-platform and cache consistency verification.Aiming at the problem that the third-party reference model cannot achieve dual-core instruction level accuracy,the reference model comparison system reconstructs the third-party reference model,optimizes the timing accuracy of the model,and accurately and efficiently completes the dual-core register and PC value verification.Researched the forwarding mechanism and internal standard conversion rules,revised the floating-point reference model,built a floating-point module sub-verification platform,and realized the automatic verification of floating-point registers and control signal checking.Aiming at the problem of cache consistency,the cache consistency verification system has constructed a set of BOOM-based cache consistency judgment rules to automatically check the cache consistency in all levels of cache.Compared with the original test set,the code coverage of the random test generated by the random instruction generation platform was increased from 79.87% to 91.92%,and the function point coverage was increased from 62.1% to 100%.The simulation speed of the verification system was increased from 600/min to 2000/min.The verification method is expanded from instruction self-checking to reference model comparison,consistency assertion,and floating point verification.Under the same test incentive,the number of BUGs that can be judged is increased from 7 to 21.The efficiency and completeness of verification have been greatly improved,meeting the verification objectives..