Research Of Design, Verification And Application For Configurable RISC Core

With the development of the semiconductor technology, the market rate of 32bit embedded microprocessor is rising. Enhancing the data processing and embedded configurability is the research hotspot. According to that, a 32bit configurable media-enhanced RISC microprocessor RISC32 (RISC3201 and RISC3202) is designed for media processing and system controlling.Microprocessor design based on IP cores has deduced the development time, but how to control the IP cores and use them effectively have been the problems. Based on IP cores processor design, the paper introduces some principles of the instruction set design and the pipelines are spilt through the ISA and the micro architecture of RISC3201. Then the control strategy of pipeline including PC controlling, pipeline controlling and data bypassing controlling are presented. The SIMD extended design is implemented in RISC32 microprocessor. Using RISC3201, a dual-core and dual-issue microprocessor RISC3202 is constructed. The pipeline controlling, data bypassing and the configurable design are discussed in the paper.With the enhanced of microprocessor functions, the microprocessor design is more and more complex, and the verification becomes more and more difficult. In the paper, a co-simulation and verification platform---MISP-Ⅱ based on FPGA is design for the simulation and verification of RISC32 processors. Based on MPSP-Ⅱ, a design method of software and hardware co-simulation and verification environment is presented. Using peripheral software design method, the configurability of software platform is implemented. Using improved bus architecture oriented to multimedia processing, the reusability of hardware platform is implemented. Through reconfiguring the software and hardware platform quickly, the MPSP-II can be applied in some simulations and verifications of different media processors, which is dedicated the MPSP-II can be used commonly. The problem of FPGA debugging is solved and the visual debugging interface is implemented through communicating between software and hardware platform. The simulation for RISC3201 is sped up to more than 10,000 times based on the MPSP-II than Modelsim.Oriented to multimedia applications based on microprocessor RISC3201, a software and hardware co-design method of MPEG-4 AAC LC (Advanced audio coding, Low complex) decoder based on RISC3201 is presented in this paper. The calculation of the decoder is deduced through system-level and assembly-level optimization, and the RISC3201 is configured based on the optimization. A simulation environment of the decoder is constructed quickly on the MPSP-II. The result indicates that the decoder requires 25.51 MIPS to decode 128Kbps, 44.1KHz 2-channel AAC LC with TNS (Temporal Noise Shaping) in real-time and the average CPI is 1.29, which is indicates that RISC3201 is configurable and the core can be used easily as an embedded microprocessor core.The 32bit configurable media-enhanced microprocessor RISC3201 has been used in multimedia digital audio and video decoding SoC chip as an embedded microprocessor core. The chip has been taped out successfully with the technology of SMIC 0.18um and can be used in system controlling and decoding audio in real-time.