High-throughput LDPC Encoding And Decoding Algorithm And FPGA Implementation

The low density parity check(LDPC)code is a class of error-correcting codes that approaches the Shannon limit,and it is also one of the hot research topics in channel coding.LDPC code can be decoded in parallel,which shortens decoding delay,facilitates hardware implementation,and has great advantages in the case of medium and short code lengths,so it is adopted by many communication standards,including Digital Video BroadcastingSatellite Second Generation Extension(DVB-S2X),IEEE802.11 ac and 5th-Generation New Radio(5G NR).With the continuous development of LDPC coding technology,more stringent requirements are placed on data transmission capability and reliability.Therefore,research on high-speed transmission technology for wireless communication is very necessary.The main contributions of this thesis include:Firstly,in view of the fact that most existing LDPC decoding algorithms have problems of high implementation complexity or poor performance,this thesis proposes a normalized min sum decoding algorithm based on least squares to improve the complexity-performance problem.The simulation results show that compared with the offset min sum algorithm,the proposed algorithm has a performance gain of 0.3d B when a small amount of multiplication is added;compared with the normalized min sum algorithm,the proposed algorithm can get an additional 0.2d B performance gain only a small amount of addition operation increased.Secondly,this thesis studies the multi-channel LDPC encoder for DVB-S2 X standard to improve its throughput.Based on serial LDPC encoder,a multi-channel LDPC encoder structure with shared memory resources is proposed through reasonable resource multiplexing and implemented in hardware.The synthesis results show that the throughput of the proposed multi-channel LDPC encoder is four times that of the single-channel encoder,reaching 1.2Gbps,and compared with the traditional four-channel independence encoder,Random Access Memory(RAM)resource consumption is reduced by 17.4% under XC7VX690 T.Finally,towards the problem of low throughput of most LDPC decoder structures,this thesis designs a layered parallel decoder structure based on the Quasi Cyclic-LDPC(QC-LDPC)code of IEEE802.11 ac.Furthermore,based on this structure,a multi-channel QC-LDPC decoder is designed and implemented with Field Programmable Gate Array(FPGA)through resource reuse.Through synthesis and simulation of the decoder,the results show that the maximum working clock frequency is 265 MHz,and the multi-channel decoder designed can achieve throughput of 2.6Gbps.