Design Of Controller For 16Gbps SerDes

With the advancement of integrated circuits and the continuous development of information technology,the information processing capability has been continuously improved,and the communication bandwidth has been continuously increased.Traditional parallel interfaces have been unable to meet the requirements for higher-speed communication bandwidth.SerDes architecture has become a key technology for high-speed I/O interfaces.In this paper,based on a self-developed SerDes chip,a controller adapted to the SerDes is designed to complete the switching of SerDes power on,speed mode,and power consumption mode;the register space and read and write logic are designed to provide register access for SerDes.Built-in self-test module and corresponding data path are also designed to facilitate SerDes testing.(1)After analyzing the structure and working principle of SerDes,The SerDes power-on strategy is determined,and the design of the SerDes power-on and rate mode switching circuit is completed.According to the power consumption mode of the PCIe protocol,the control signal values of the four power states are determined,and a power state conversion circuit is designed.(2)Register space and register logic circuits are designed for SerDes.Most functions of SerDes can be controlled by rewriting the registers,and SerDes working status information can be obtained by reading the monitoring registers,which improves the configurability and monitorability of SerDes.(3)In order to solve the problem of SerDes chip test difficulty and ensure the accuracy of data transmission,a built-in self-test module is designed for SerDes.This article designs a Pseudo-Random Binary Sequence generator with variable bit width and configurable random pattern,and adopts a multi-cycle synchronization mechanism to complete the synchronization comparison.A responsive data path is also designed to support normal data transmission and loopback detection of SerDes.(4)In order to verify SerDes and the controller globally,we extracted and built the Verilog model of SerDes and built a verification environment based on Verilog.The correctness of the overall function of the controller is verified by using NC-verilog.Finally,we synthesized the design on the UMC 28 nm CMOS process and analyzed timing,area,and power consumption of the SerDes controller,which met the requirements.