Research Of Low-Power Design Method Based On SOC Test Controller

In recent years, semiconductor technology and integrated circuit system design developed rapidly, system-level chip is becoming the mainstream of large integrated circuits step by step. SOC usually has to integrated multiple completely designed IP core with composite module, complete increasingly complex logic functions to reduce design cycle of system chip, but has brought unprecedented complexity degrees for chip tested. When the IP core embedded in the SOC, each pin can not all leaded to the external, so the IP core which used could be measured became unpredictable. A key issue of SOC test. is how to use the outside pin to test the original port of each IP core. With the continuous expansion of SOC function, the text reuse of the IP core is the core of test structure design related to SOC chip. SOC test power consumption became the key issues that developers need to consider. How to combined low-power techniques and test structures will be the key issue of SOC design in the future.The paper begin with the test structure, and treat ITC02benchmark circuit as a test object, to build the test model of the SOC, which included test shell, test access mechanism and test controller of test shell. In order to achieve the SOC optimized low power design of test controller, the paper start from the optimization of the hardware structure, to use the theory of the test scan chain transformation and circuit partitioned to reduced the average power consumption and peak power consumption in order to optimize power consumption. The test controller is the total scheduling in the testing process, to reduced system testing power consumption furtherly by optimized the test controller, and to use innovative parity dl descending order algorithm to rearrange the order of the test vectors in the process of testing. to reduced all nodes transitions to the adjacent test vectors in order to reduce the total jump variables to achieve system low-power test ultimately. The test program based on Altera Corporation Quartusâ…¡9.0software, using verilog digital description language to describe and establish a standard test shell structure and test system, compared the power consumption of the test program before optimized with after,the results indicate that several kinds of test optimization program can reduce the power consumption in the testing process.