Research On Key Technologies Of MASH 2-1 SAR VCO ADC

The rapid development of the mobile Internet era has created unprecedented opportunities for the application of wearable and portable devices,and has also promoted the maturity of the fifth generation of mobile communication technology.The main advantages of 5G networks are fast data transmission rates and low latency.As the most important component of communication technology,the analog-to-digital converter(ADC)is becoming more and more stringent in terms of power consumption and performance.The research emphasis of ADC is to improve the conversion accuracy and bandwidth and reduce the power consumption,which limits the market application value of the ADC.As a new ADC architecture,noise-shaping SAR ADC has received more attention,since it can achieve higher accuracy than traditional SAR ADC and save power consumption compare to traditional Sigma-Delta ADC.With the progress of semiconductor technology,the characteristic size of transistors is getting smaller and smaller,which makes ultra-low voltage design possible,but it also brings difficulties to the design of traditional voltage domain quantization ADC.The VCO quantizer is used to convert the voltage signal into a time domain signal,and the analog signal is converted into a digital signal by the phase integral quantization,which can effectively solve the above problems.The VCO quantizer is mainly implemented by digital logic circuits,with low power consumption and great process compatibility.Therefore,in this paper,combining the characteristics of noise shaping SAR ADC and VCO quantizer,a MASH 2-1 SAR VCO ADC structure is adopted,in which noise shaping SAR ADC serves as the first stage and VCO quantizer serves as the second stage.The main content of research are as follows: Firstly,in order to achieve an ideal two-order noise shaping structure and improve the quantization accuracy,a two-order NS SAR ADC based on dynamic operational amplifier for lossless integration is built.A high-level model of a two-order noise-shaping SAR ADC is established using mathematical methods.The results of MATLAB simulation verification show that the lossless integration network has good noise shaping effect.In order to further improve the integrity of the non-destructive integrator,a PVT insensitive complementary dynamic operational amplifier is used to realize the fixed gain.At the same time,using the Ping-Pong structure to complete the integration loop,which effectively reduces the area of the integration capacitor and saves power consumption.Finally,the corresponding circuit design was completed,and the validity of the design was verified by Cadence simulation.Secondly,the VCO quantizer structure based on a ring oscillator is used to further quantify the first-order quantization residual in the time domain.With VCO model,the feasibility of phase integral requantization was analyzed mathematically.The behavior model of VCO quantizer was built through Simulink,and the simulation results show that VCO quantizer can implement the quantization function perfectly,at the same time,it has first-order Noise shaping characteristics.On the basis of this,the VCO quantizer is combined with the twoorder noise-shaping SAR ADC to improve the noise shaping effect of the whole circuit.As the second quantization unit,VCO quantizer has a small quantization range(～m V level),which avoids the linearity problem.Furthermore,the mathematical model of the delay unit is analyzed,and the mechanism that the main factor affecting the VCO oscillation frequency is the charging and discharging current of the delay unit is obtained.Then,a high linearity voltage-to-current circuit is designed,which can control the delay time of each delay unit by mirror current,and effectively control the oscillation frequency of VCO.Simulation results show that the structure has better quantization characteristics.Finally,using TSMC 65 nm process and based on the Simulink MASH 2-1 SAR VCO ADC structure,the whole circuit was designed,including key modules such as sample-and-hold circuit,six-input dynamic comparator,complementary dynamic amplifier,VCO quantizer,then the physical layout is drawn.Simulation verifies the correctness and feasibility of the design.With a power supply voltage of 1.2V,a sampling frequency of 100 MHz,and a signal bandwidth of 6.25 MHz,SFDR = 103.6DB,SNDR = 82.8d B,ENOB = 13.46 Bit,and power consumption are 1.6mW.