Research And Implementation Of Instruction Hardware Prefetch Based On BOOM

Modern processor front-ends mainly fetch instructions from the instruction cache.Limited by the waiting time of the query cache and other factors,the capacity of the first-level instruction cache is often limited.Therefore,a cache miss will inevitably occur in the fetch request of the front end,and the jump behavior of the program branch instruction further increases the probability of this phenomenon.When a cache miss occurs,the instruction cache will initiate a request to the lower-level storage to obtain instruction data,and the processor front end will stop working.Instruction prefetch technology has been proven to reduce the impact of cache misses very well.Decoupling the front end and using the results of branch prediction to guide the execution of instruction prefetch is a scientific and effective method.The main work of the paper is as follows: 1.Completed the design of the front-end decoupling queue based on the Berkeley open source chip BOOM.The decoupling queue continuously receives the prediction results of the front-end branch predictor when the instruction cache is blocked.These results can be used to guide the execution of instruction prefetch.The paper has completed the design of the storage contents of decoupled queues,control pointers such as fetch instructions and prefetch instructions,global control logic such as queue blocking or refresh,and timing design of decoupled front ends.And simulation verified correctness of the decoupling design.2.Completed the design of the instruction prefetcher based on the decoupling front end.Modified the state machine and blocking control signal of the instruction cache to allow the instruction cache to receive the request address in the decoupling queue when a request miss occurs,and perform cache probe filtering to filter the prefetch addresses.A prefetch address queue is designed to store the filtered prefetch addresses and initiate a prefetch request while the instruction cache is working normally.In order to avoid pre-fetching data from contaminating the instruction cache,a stream buffer is designed to store the instruction data obtained by pre-fetching.Each time the processor fetches instructions,it will search the instruction cache and pre-fetching stream buffer at the same time.The Tile Link bus connection between the prefetch stream buffer and the instruction cache is designed to ensure the correctness of data transmission.The execution results of test programs such as SPEC2006 were calculated through simulation.The effect of different decoupling queue lengths on the prefetcher was compared,and the length of the queue was finally determined to be 16.The prefetcher designed by the paper improves the running speed of BOOM by 7.3%,and the average accuracy of prefetching is 88%.