Research And Implementation Of High Performance Elliptic Curve Cryptographic For IoT Security

In today’s society,with the rapid development of the Internet of Things,potential safety problems also follow.For example,Io T terminals are attacked due to the lack of identity authentication mechanism,and because of the insecurity of the transmission channel,the key is lost,which often leads to information leakage.Therefore,relying only on symmetric encryption algorithms cannot meet the security requirements of the Internet of Things.The digital signature protocol derived from the public key cryptographic algorithm can be used for identity authentication.The key exchange protocol can generate a key known only to the communication parties on an insecure transmission channel,and this key is generally used as the key of subsequent symmetric encryption,so the public key cryptographic algorithm can provide a reliable guarantee for the security of the Internet of Things.Among them,SM2 algorithm,which is based on ECC elliptic curve mechanism and has developed security protocol standards in the fields of digital signature and key exchange,meets the security requirements of the Internet of things very well.This thesis firstly researches the elliptic curve cryptographic algorithms related to digital signature,key exchange,encryption and decryption,and analyzes the mathematical operations common to these algorithms: the concept of finite fields,the definition of elliptic curves,related operations of points defined on an elliptic curve and so on.When designing the algorithm implementation,if the pure software design method is adopted,the computing efficiency and security are poor;if it is implemented by pure hardware,the area resource consumption is large,and it is not suitable for the application environment of the Internet of Things.Then,in order to enhance the flexibility of the system and improve the computing performance,in this thesis,the method of software and hardware co-design is used to design elliptic curve cryptography algorithm,and this thesis designs the overall architecture of the system: a hardware coprocessor to improve the module’s operation efficiency;software calls hardware modules to complete the overall process of the algorithm.According to the requirements of application scenarios,the algorithms of each operation layer are optimized accordingly.At the same time,corresponding hardware implementation schemes are provided.Considering the resource and power requirements of the Io T application environment,methods of time-sharing multiplexing and pipeline are integrated into the circuit design.After completing the RTL-level code design,functional verification is performed on the elliptic curve cryptographic algorithm by Modelsim software.At the same time,the FPGA performance test is performed on the circuit based on the FPGA board DE4 development board of the Stratix IV GX series of Altera Corporation.Finally,the implementation of the circuit ASIC is based on the standard cell library of Grace’s 110 nm process.From the test results,the design can reach a clock frequency of 106 MHz.The circuit occupies242170.36μm2,about 59 k equivalent gates.After comparative analysis,the design of this thesis has certain advantages in computing performance and area,supports dual finite field computing,and is suitable for resource-constrained environments such as the Internet of Things.