Design Of Low-jitter PLL For High-speed Serial Interconnection

With the increasing of communication frequency and transmission distance,the parallel transmission mode of traditional communication has some problems such as data crosstalk and clock skew,which seriously affect the communication quality.At present,SerDes interface of high-speed serial technology is becoming a popular research direction due to long transmission distance,high reliability,and high integration.It is widely used in the fields of communications and computers,and realizes the interconnection between chip and optical module,chip and Ethernet.It is foreseeable that with the rapid development of modern information technology,high-speed SerDes technology with the rapid development of communication protocols will have unlimited potential for development.As the provider of the highest clock in SerDes system,the high frequency and low noise performance of PLL frequency synthesizer determines the speed and quality of system data paralledl-toserial or or serial-to-parallel conversion,so the high performance research of PLL is also important.This thesis implements a low-jitter PLL circuit for high-speed serial interconnection.The circuit is used in a 28Gbps SerDes system with an output frequency of 14GHz to provide the highest working clock for the transmitter and receiver.PLL system design includes the anolog circuits of LC oscillator,phase frequency detector,charge pump,low-pass filter,and the digital-analog mixed circuit of fractional divider.This thesis completes system digital-analog mixed simulation and back-end layout design and optimization.The proposed LC oscillator uses cross-coupled pair of cross-drain resistance,which can suppress flicker noise,and capacitor array structure which can adjust center frequency to meet the design requirement of low phase noise and wide frequency band.The fractional divider uses a MASH 1-1-1Σ-Δmodulator technology and a multi-mode frequency divider to realize an average fractional frequency division.The proposed 8/9dual-mode frequency divider is based on source coupling logic latch,and introduces theπ/2 module to select the I-channel output of trigger,which reduces the overload parasitic effect and is suitable for the working requirement of hign frequency band.The proposed PLL circuit is based on TSMC N65nm CMOS process and the power supply voltage of 1.2V,which can work normally at all temperatures and process corners.Under the standard simulation environment of tt corner and 27° temperature,the output frequency range of LC oscillator is 9.5GHz～14.8GHz,and the phase noise at 14GHz is-103d Bc/Hz@1MHz.When the output frequency of PLL is 14GHz,the peak-to-peak jitter is 15.8ps,the lock time is 5.2μs,the system power consumption is 32.77m W,and the layout area is 650μm*730μm.