Partial-scan-based Emulation Method Of Fault Injection Attacks On Integrated Circuits

With the improvement of social informatization and the breakthrough of intellectualization,the role of integrated circuit industry in social development is becoming more and more important.As the cornerstone of all kinds of electronic systems,the security of integrated circuits is the basic guarantee of all information and intelligent equipment.Fault injection attack is an effective and common method to lead circuit information.Fault injection attack decodes key of encrypted circuit by inducing circuit fault,which is very aggressive and harmful.Therefore,before chip commercial producing,it is necessary to evaluate the ability of designed circuit against the fault injection attacks.At present,fault injection attack simulation methods mainly include chip-based test,software-based simulation and hardware-based emulation.Chip-based test has high cost and long cycle.Therefore,it is necessary to mimic the fault injection attack and evaluate the ability of the designed circuit against fault injection attack at design stage.The software-based simulation runs slowly,and the time overhead is very large with large amount of fault model data.Hardware-based emulation can provide efficient method.Hardware-based emulation paltform is implemented in FPGA,which is similar to integrated circuit.In the available hardware-based emulation,logic overhead is the problem of this method.Therefore,a partial scan method is proposed to reduce overhead of hardwarebased emulation.Available partial scan methods cannot be applied to hardware-based emulation directly.In order to realize the partial-scan-based emulation of fault injection attacks on integrated circuits.Our efforts involve the following aspects.Fisrt,a FPGA-based hardware platform for fault injection attack is proposed,which composed of control module and data transmission module.Second,a partial-scanbased circuit state control method is proposed.The method extends the balanced structure method,and divides DFFs of circuit into groups,and control each group one by one.The experimental results of ISCAS benchmarks circuits show that compared with the full scan,the proposed method reduces the number of scan flip-flops by 28.04% on average.Finally,data transmission between PC control terminal and FPGA executive terminal is realized.The method realizes the Partial-scan-based emulation of fault injection attacks on integrated circuits,and effectively reduces the logic overhead.