Design And Implementation Of Radar If Signal Preprocessor Based On FPGA

The current radar system has a high requirement for real-time processing of signals,but the processing capacity of the existing signal processors cannot match the high signal data rate after sampling at the front end of the radar system,thus the radar signal preprocessing technology is generated.The high data rate signal sampled by the front end of radar system by Analog to Digital Converter(ADC)is processed by the preprocessor of radar if signal mixing,sampling downsampling,clutter filtering and pulse compression.When the traditional preprocessor completes the above functions,it fails to take into account the consumption of resources and the problem of computing speed,which leads to the low performance of the preprocessor.In this thesis,based on software Radio(Softwarre Defined Radio,SDR)thought,adopting Field Programmable logic Gate array(Field-Programmable Gate ’Arry,FPGA)technology has completed the design of the radar intermediate-frequency signal preprocessor,is moved in the realization of frequency spectrum of the signal data rate reduce,digital filter and pulse compression,and other functions of mixing,filtering module has been optimized,in order to enhance the preprocessor performance.In this thesis,the basic theory of digital signal processing is introduced in detail,and the implementation algorithm and structure of NCO,CIC,FIR and pulse compression of preprocessor are studied in depth.Then Quartus II 13.0 and MATLAB were used to complete the model design of the preprocessor,and improvements were made to the mixing module NCO and filter module FIR.Among them,NCO adopts the pipeline structure of 16-level CORDIC algorithm,and expands the calculated data bit to 16 bits to improve the algorithm’s operation accuracy and reduce the resource occupancy rate.FIR uses the parallel DA algorithm based on the structure of the search table instead of multiplication and accumulation operation,4 segmentation of the search table,to ensure the processing speed of FIR while reducing the consumption of ROM resources.Through Modesim and MATLAB to simulation,this thesis designed the preprocessor and download to Altera Cyclone Ⅱ EP2C35F672C6 chip in analyzing the performance of the preprocessor.The experimental results show that the preprocessor designed in this thesis saves 25% of the hardware resources compared with similar designs,and its computing speed is up to 434.79 MHz with the overall performance improving by 23%.This design can reduce the hardware resource consumption and improve the computing speed while processing signals in real time,and is suitable for radar signal processing.