Study On Reliability And System Optimization Of 3D NAND Flash

In the past decade,non-volatile storage market has grown dramatically.Benefitting from the good seismic performance,high integration density,excellent reliability and many other advantages,NAND flash has already become the mainstream storage medium of non-volatile storage field.Two-dimensional(2D)NAND flash improve the storage density by adopting downsize.With size scaling down,2D NAND flash suffers continuous reliability degradation and when the physical size shrink to a certain node,the reliability problem will completely be out of control.To overcome the bottleneck,three-dimensional(3D)stackable NAND flash architecture has been accepted and applied.3D NAND flash has significant superiority compared with 2D NAND flash,but its reliability degradation mechanism is more complicated.In this paper,we carry on some studies about charge-trap(CT)3D NAND flash reliability and storage system optimization,and proposed corresponding solutionsThe first part is 3D charge-trapping NAND flash reliability research of open block scene.Open block is one of the special situations during the usage of 3D NAND flash.It contains both programmed word-line(WL)and unprogrammed WL.In open block,for this WL that has been programmed but its next WL is not programmed,we name it as edge WL.Because of the lateral charge diffusion,edge WL has poor reliability performance.According to the experimental data,in case of read after programming and data retention for 12 hours,the bit error rate(BER)of edge WL in open block is?2.6x and?4.0x of other programmed WLs.Based on the previous work,we applied multiple read operations to the edge WL.In the data retention scenario,we found that the average BER decrease 56.40%between the first read and second read,but there was no significant reduction of BER after the second read operation.Hence,we proposed extra-read reliability recovery scheme which refers to applying two read operations on edge WL of open block.Depending on the recovery reason of extra-read scheme,we programmed the next WL of edge WL,which is called dummy WL(DWL)in this paper.After programming,the average BER of edge WL decreased by 82.01%in comparison with the BER without any recovery scheme.Therefore,we proposed extra-program scheme which refer to programming DWL.We made a tradeoff for two schemes of recovery between decoding efficiency and error correction capacity of the two recovery scheme and system overhead caused by them in NAND flash controller,and finally optimized the decoding process of 3D charge-trapping NAND flash open block edge WL.Then we studied the relationship between data pattern in DWL and edge WL data retention feature.According to the result of measurement,we could conclude that when the data pattern written into DWL corresponded to a higher threshold voltage,the data retention characteristic of edge WL are better.The second part is research on optimal read voltage determination method of NAND flash.Based on the error features of 3D charge-trapping NAND flash during data retention,this paper proposed a new optimal read voltage determination scheme.We have performed Gaussian function fitting on the threshold voltage distribution of flash memory in order to collect the mathematical parameters of threshold voltage distribution under different conditions.By importing the basic parameters and Gaussian distribution mathematical parameters for executing the optimal read voltage scheme,we can estimate the optimal read voltage position,and use the deviation between the estimated position and the ideal optimal read voltage position as the accuracy criterion.The analysis and test results show that the optimal read voltage determination scheme proposed in this paper consumes less additional system overhead compared with traditional scheme.It has high estimation accuracy to decrease the read error significantly,and gives consideration to the storage system efficiency and reliability performance.