Research On Characteristics And Optimization Of Charge Trap 3D NAND Flash

As storage represents one of the three pillars of IT infrastructure,its rigidity has considerably impacted the development of the information industry.In this context,Solid State Drive(SSD)based on NAND flash memory has emerged as a priority storage device due to its exceptional performance.With the growth of the digital economy,the data storage market has continued to expand,necessitating the development of new technologies to increase the capacity of NAND flash memory.Engineers have thus developed multi-bit storage,crystal process technology,and three-dimensional stacking technology to enhance storage density.In the current market,3D NAND flash has become the dominant medium;however,as storage density increases,the challenge of data reliability for 3D NAND flash becomes more severe due to the unique 3D structure and different materials used for storage units.Ensuring high data reliability is therefore a critical factor for the widespread application of 3D NAND flash.Accordingly,this thesis aims to investigate an error optimization scheme to improve the reliability of data for 3D NAND flash.The first part focuses on the data retention of charge trap 3D NAND flash.A simulation using the Arrhenius accelerated model is employed to study the real retention of 3D NAND flash by baking at high temperatures for a specific time under laboratory conditions,and the retention errors in different program/erase cycles and layers are analyzed.Two types of charge loss modes that cause errors are identified based on the flash unit structure.To suppress lateral charge loss,a Data Pattern Pre-program and Hold(DPPH)scheme is proposed to optimize data retention.Experimental data demonstrate that the proposed scheme can reduce error bits by up to 33% in the data pattern with low threshold voltage difference.The second part focuses on the open block of charge trap 3D NAND flash.The error distribution of open block characteristics and the error variation of the edge Word Line(WL)in different layers are analyzed experimentally.The special position of the edge WL is analyzed,and the reason for the error is attributed to the negatively offset cell voltage distribution of the storage unit,which increases the number of errors and produces the open block phenomenon.A read voltage optimization is proposed based on the golden section search method and the Read Offset function provided by the flash chip.Experimental data demonstrate that this scheme can enhance the characteristics of the open block,accurately locate the best reading voltage position,and reduce the number of error bits by 97%.