Design And Implementation Of Teaching Model Machine Based On RISC-V Instruction Set

Computer Composition Principle is an important professional basic course related to computer science,which is composed of two parts : theory and experiment.The design experiment of the controller is an important part of the application of theoretical knowledge.In the traditional teaching experiment,students can only observe the experimental results through the experimental box,and can not easily see the problems existing in the design.If the debugging system is added to the experimental link,students can see the data change process inside the model machine,and find the problems existing in the design of components,data paths and controllers.RISC-V instruction set architecture is short,coding specification,solve the problems existing in the previous instruction set,RV32 I is the core of RISC-V instruction set.Therefore,this paper designs and implements a teaching model machine based on RV32 I.This dissertation first introduces the process of using Verilog HDL to design single-cycle and multi-cycle model machines based on RISC-V instruction set on Vivado development software,including the design of data path and controller of model machines.Then,the debugging system is designed,and the debugging interface is added on the basis of realizing the basic functions of the model machine.The control and debugging of the model machine are realized through the communication between the state control module and the debugging software.The state control module controls the working state and debugging mode of the model machine;The debugging software functions include sending debugging commands,receiving data during the running of the model machine and displaying them on the PC side.The debugging software is compiled by C++ programming language in QT development environment.The simulation results of the sample program in the model machine are given in this dissertation.The functional simulation results show that the sample program can be correctly executed in the model machine.Finally,the process of testing the model machine through the sample program on the Nexys 4 DDR FPGA development board is explained.The results show that the state control module and debugging software can be used to debug the model machine.