Realization Of SDH Simulation Tester Based On FPGA

SDH communication network infrastructure,equipment R&D,operation and maintenance,these continue to increase the demand for SDH testers.However,the existing domestic SDH testers still have the problems of poor portability,slow processing speed,and not suitable for high-speed transmission links.Therefore,optimizing and improving the SDH tester is essential to improve the quality of SDH communication network service.This article aims to improve the current lack of SDH testers and innovatively proposes the design of an FPGA-based SDH simulation tester,the main innovations and work of this article are as follows:(1)Propose hybrid parallelization technology suitable for FPGA.According to FPGA pipeline and parallelization mode,hybrid parallelization technology is proposed.Then,the possibility of implementing hybrid parallelization technology on FPGA is demonstrated from three aspects:research foundation,design mode and evaluation criteria.(2)Build a hybrid parallelization model based on FPGA.Aiming at different types of streaming data operations,three FPGA-based hybrid parallelization models are proposed to solve their problems.Abstract the operational logic on the FPGA as a collection,construct three FPGA-based hybrid parallelization models based on non-inhibited parallelism and correlation between subsets:Single-stage rolling pipeline model,pipeline merge tree model,and map-merger tree model.(3)Design and Implementation of SDH Simulation Tester Based on Hybrid Parallel Model.First introduce the overall scheme of the FPGA-based SDH simulation tester.Then the single-stage rolling pipeline model,pipeline merge tree model and map-merger tree model are applied to the design of synchronization technology,PRBS algorithm and scrambling algorithm respectively,achieved an increase in the rate of key technologies.Then perform functional simulation and timing simulation on the SDH simulation tester,verify that the design meets the international ITU-T G.704 and ITU-T G.707 standards.Finally,the performance of the SDH simulation tester is evaluated and analyzed from the three aspects of delay,throughput and resource usage.It is known that when the resource usage is reduced,the delay performance of the improved logic circuit is increased by about 4%,and the throughput is increased by 4 to 8 times.It is proved that the design can effectively improve the overall performance of the SDH simulation tester.