Design Of A Physical Verification System For Channel Codec Performance Of Embedded WEB Architecture

Channel codec algorithm is an important technique to ensure reliable transmission of communication data in digital communication systems.In the process of compiled code algorithm research,system modeling and analysis of compiled code algorithm using simulation technology is an important tool to help researchers measure the performance of the algorithm.Computer simulation is affected by computer performance,and it is difficult to cope with large data volume and high precision simulation;usually the verification model based on physical simulation technology is difficult to develop,and the system versatility and model reconfiguration ability are not strong.Semi-physical simulation technology has strong flexibility through hardware-in-the-loop and software-in-the-loop,and has wide application value in the communication field.However,the current semi-physical systems for channel compiled code verification are mostly based on the mechanistic implementation of Simulink programmable FPGA,which are difficult to generalize and adapt to the performance verification of user-developed hardware algorithms.This paper adopts the idea of semi-physical simulation and design an embedded WEB architecture with remote sharing for the physical verification of channel compiled code performance based on ZYNQ series development platform to address the problems of difficulty in developing a fast verification system for channel codec hardware algorithms and insufficient versatility and model reconstruction capability.This paper provides a solution to the problem of rapid verification of the performance of channel codec algorithms for hardware-oriented algorithm researchers.This paper uses a single-chip ZYNQ heterogeneous processor architecture to deploy the system hardware and software functions,solving the problem of low cost and miniaturization.The solution uses FPGA as the hardware platform to design a generalized hardware architecture for the verification system,which provides users with generalized open IO to support fast access to hardware algorithms and build verification models;the embedded control software with WEB architecture is designed using the ARM architecture processor as the control center of the verification system to realize remote sharing and control of the system by users,manage the configuration of verification models and the embedded control software with WEB architecture is designed to realize remote sharing and control of the system by users,manage the configuration of verification model and online customization of verification process.In this paper,software and hardware communication protocols are designed to solve the problem of hardware and software working together in the compiled code verification system.The key technologies are analyzed and solutions are given for the key problems in the system implementation.This paper gives the detailed design implementation of the generalized hardware architecture of the verification system,and designs a remote online reconfiguration function for the remote configuration problem of the system;designs a generalized data scheduling architecture for adapting the data rates and interfaces of different compiled code algorithms;designs a compiled code performance verification model for the access problem of user hardware algorithms,and provides a generalized open interface of compiled code algorithms,which users A channel model is designed to solve the construction problem of compiled code algorithm verification environment.The detailed design and implementation of the embedded control software of the system WEB architecture is given,and the embedded WEB server is designed to realize the remote shared access of users;the visual control web page and program are designed to realize the visual control of the system by users.Finally,the completed system was tested,and the RS code and convolutional code required by the project were selected to access the hardware architecture,and the verification model was constructed and configured to complete the test.The test results show that the system can quickly access different channel compiled code algorithms,build verification models,support online configuration of multiple application scenarios,realize remote verification of the performance of compiled code algorithms,and the system is highly reliable and can support BER statistical accuracy of 1e^-9 magnitude,which meets the system index requirements and completes the project delivery.