The Design Of Analog-to-digital Converters With New 2.5-bit/cycle Conversion Technique

With the development of CMOS process,high-performance ADCs have been widely used in the fields of wireless body area network(WBAN),Internet of Things(Io T),image sensor and wireless communication.Conventional successive approximation analog-to-digital converter(SAR ADC)has the advantages of low power consumption and simple design,but its conversion rate is slow.So it is suitable for low-medium-speed and medium-resolution applications.Pipeline ADC is widely used in high-speed and high-resolution applications because it can achieve both high resolution and high speed,but its power consumption is very high.To improve the conversion rate of SAR ADC,this paper has proposed a new 2.5-bit/cycle conversion technique.Based on this technique,a 7-bit50MS/s SAR ADC has been designed for the low-resolution high-speed applications and a 14-bit 40MS/s Pipeline-SAR ADC has been designed for the high-speed high-resolution applications.In addition,this paper has implemented a butterfly randomization algorithm to improve the linearity of high-resolution Pipeline-SAR ADC.Implemented in XFAB 0.18-μm CMOS process,under 1.8V supply voltage and 50MS/s sampling rate,the post-simulation results show that the SAR ADC has achieved the ENOB of 6.63 bits,the SFDR of 58.3d B,the Fo M of 327 f J/conv-step with the power consumption of 1.63 m W.Implemented in XFAB 0.35-μm CMOS process,under 3V supply voltage and 40MS/s sampling rate,the pre-simulation results show that the PipelineSAR ADC has achieved the ENOB of 13.8bits,the SFDR of 96.4d B,the Fo M of 0.19 p J/conv-step with the power consumption of 110 m W.