Accelerator Design Of FPGA Target Detection Algorithm Based On Vitis

The development of artificial intelligence technology is more and more rapid.Target detection is one of the most widely used artificial intelligence technology,and there are still better methods in this field.At present,most target detection products are deployed on GPU platforms or traditional CPU machines,and the detection efficiency of CPU is relatively low,while GPU has the disadvantages of large power consumption,non-reconfiguration and high cost.Compared with GPU,FPGA has the advantage of being reconfigurable.The hardware is designed according to the actual demand,with low power consumption and better heat dissipation performance.FPGA has been widely used in real-time image processing,signal processing,medical aviation and other fields.In this thesis,the DF-Retinaface algorithm is an improved design of target detection algorithm based on Retinaface deep learning algorithm,and a target detection accelerator based on FPGA programmable platform is designed for the convolutional neural network.The specific operations are as follows: Aiming at the problem that FPGA is not suitable for processing floating-point numbers,INT8 fixed-point quantization operation is adopted to customize the algorithm model,and the 32-bit floating-point model is converted to 8-bit fixed-point model;Aiming at the problem that the quantization operation will lose a little precision of the algorithm,a new improved network structure is proposed to improve the detection effect of the algorithm model,and simplify the setting of the prior box and activation function to improve the speed of training and prediction;The DPU(Deep Learning Processor Unit)with maximum parallelism is adopted for the rich logical resources of FPGA,and the higher throughput rate is achieved by improving resource utilization.In view of the characteristics of the Vitis unified platform tool and FPGA,the Vitis acceleration library kernel is used to accelerate the image scaling and format conversion in the processing process.In this thesis,the Tensor Flow framework and the ZCU102 hardware platform were used to implement,train and test the algorithm,and the experimental data were compared and analyzed.The experimental results show that multi-task supervision can improve the detection effect of the algorithm model.The fixed-point quantization operation can significantly reduce the size of the algorithm model,which is about one quarter of the previous size,and reduce the resource consumption.FPGA detection is about 9 times faster than CPU.The improvement of network structure can improve the detection effect of medium and large targets.The acceleration of algorithm preprocessing can reduce the time required for preprocessing,and the image scaling and format conversion kernels reduce the time of single image preprocessing by about 1 times.In addition,the energy consumption of detecting a single image on FPGA platform is only 10.5% of that on GPU platform,which proves that FPGA has a huge advantage in power consumption.Finally,a comparative experiment with other similar work in recent years further verifies that the Vitis unified platform development method and the FPGA accelerator design in this thesis have higher throughput rate.