Research On Compressed Sensing Hardware Optimization And System Implementation Based On FPGA

Compressed sensing points out that the compressed signal could be sampled directly by the signal sparsity,which possesses the advantages of low sampling rate and low data storage pressure.Compressed sensing has wide application prospects in wireless sensor networks,bioelectrical signal sampling,multi-input multi-output system design and transform domain sampling system design.Since the advent of compressed sensing theory,how to design more efficient and hardware-friendly signal encoder and how to design a reconstruction algorithm with low computational complexity and high reconstruction quality has been the focus of research in this field.In this thesis,the optimal design of measurement matrix,the design of reconstruction algorithm and the hardware implementation of compressed sensing theory are systematically researched.Meanwhile,the experimental verification on electrocardiogram datasets was carried out.The results are summarized as follows:1.An efficient compressed sensing measurement matrix,named sparse binary random measurement matrix,is proposed,which can be generated by linear feedback shift register in the FPGA in real time.Compared with the traditional binary random matrix,it can not only lower the computational complexity of the encoding process effectively,but also reduce the consumption of hardware resources in chip significantly.2.A two-stage quantization compressed sensing encoder is proposed based on the combining of the approximate computation theory with the compressed sensing quantization method.Experiments on compressed sensing encoding schemes with different quantization levels are carried out.The results show that the proposed method can reduce the consumption of both storage resources and logic resources in the FPGA significantly on the premise of ensuring the accuracy of signal reconstruction.And the maximum operating frequency of the system would be improve.3.Two signal reconstruction methods based on deep neural network are proposed to solve the problem of low performance of traditional reconstruction methods.And a hardware acceleration design of FPGA for convolution neural network is further proposed.The experimental results show that the proposed signal reconstruction method has well reconstruction effect,and the hardware acceleration scheme has significant acceleration performance.