Design Of Reading And Writing Circuit For High Reliability Ferroelectric Memory

With the rapid development of science and technology,people are not satisfied with the present status of the memory and put forward higher requirements for the memory.In the case of limited progress in ferroelectric materials,in order to comply with market demand,this thesis is dedicated to the development of more reliable memory read and write circuits.This thesis first analyzes some of the reliability problems of ferroelectric capacitors,such as ferroelectric aging,fatigue failure,retention loss,memory cell MOS transistor threshold loss,etc.,and draws the following conclusions:first,the memory circuit design should minimize the repeated times of writing of the memory cell;second,the design of the memory circuit should make the time of applying forward voltage to the ferroelectric capacitor basically consistent with the reverse voltage;third,the memory circuit design needs to increase the applied voltage of ferroelectric capacitor as much as possible,such as the design of the sensitive amplifier and the board line drive circuit;fourth,it is necessary to design the word line boost circuit to eliminate the influence of the threshold loss on the applied voltage of the ferroelectric capacitor.Under the guidance of the above conclusions,this thesis has completed the design of the word line boost circuit.The word line boost circuit can drive 8 pages of memory cells at the same time and can stably eliminate the threshold loss;this thesis also completed the design of the sensitive amplifier,a pre-amplification circuit can be shared by 256 memory cells,and can amplify the bit line voltage difference to the full swing in time;this thesis has also completed the design of the plate line drive circuit,which can be shared by 16-page memory cells,and can quickly increase the plate line voltage to a level close to the power supply V_DD.Based on the completion of the word line boost circuit,the sensitive amplifier and the plate line driver design,this thesis has completed the design of the memory cell array.Since this memory does not have a clock pin,it is necessary to design a timing generator.The timing generator designed in this thesis can accurately detect the A16～A2address changes and output a series of timing signals.Using these timing signals,this thesis completes the design of the control logic module,and then completes the design of the read-write circuit,which implements read-write access to the memory cell array（including page mode access）.In order to reduce the repetitive writing times to the memory cell,the writing scheme is optimized in this thesis,and the half-page writing scheme,byte writing scheme and bit writing scheme are obtained.The half-page writing scheme reduces 39-bit repetitive writing times compared to the page writing scheme when the write access column addresses in a row address access are all in the same half page.Compared with the half-page writing scheme,the byte writing scheme further reduces the repetitive writing times to the memory cell.The bit writing scheme realizes 0 repeated writing times to the memory cell.