| In recent years,with the increasing proportion of intelligent sensors in people’s lives,multi-sensors micro system has been widely used in the word.The analog front-end(AFE)circuit of most sensors mainly includes interface circuit module and analog-to-digital converter(ADC)module.The AFE circuit is used to convert various non-electrical signals or electrically convertible signals carrying sensing information into voltage or current signals and output digital signals.The analog front-end circuit designed for specific architecture and function is not suitable for the wireless multi-sensor node system of the Internet of things,because these dedicated analog front-end can not effectively use the shared resources in the highly integrated micro system.All kinds of sensors are used in wearable intelligent devices fields,biomedical electronic devices,environmental monitoring system and smart house.Its analog front end should have the characteristics of universality and low power consumption.For hybrid circuits,the scaling of transistor size reduces the supply voltage,resulting in the reduction of the dynamic range of circuit.However,the noise can not be scaled.Therefore,the sensitivity of analog circuits to noise is increased,and the signal-to-noise ratio and other important indicators of analog circuits are reduced,which greatly limits the circuit performance.ADC is a key link between analog and digital domains,ADC should not be the bottleneck of restricting the working frequency of the whole circuit system.We must find a convenient and effective way to break through the limitation of ADC performance caused by process development.This thesis mainly introduces the following aspects:(1)The reconfigurable multi-sensors interface circuit is constructed.On the basis of switched capacitor technology,a reconfigurable multi-sensors interface circuit is realized by sharing an operational amplifier.The traditional sensor interface circuit only aims at specific sensor input type,and each interface circuit corresponds to an opamp.In this thesis,the interface circuit is reconstructed by switches,capacitors and resistors,so that multiple sensor signals share the same amplifier,which can effectively reduce the chip area and power consumption.Compared with the interface circuit based on chopper technology,this thesis is compatible with the sampling system,and has a wider input and output swing without additional filter.For voltage,resistance,current,capacitance and other sensor modes,the structure analysis and circuit simulation are carried out respectively to achieve a highly scalable universal sensor interface circuit design.(2)In order to achieve a high resolution time domain ADC,a voltage to delay cell with high linearity and wide input voltage range is established.Through the comparison and analysis of voltage domain ADC and time domain ADC,the development of time domain ADC conforms to the development of CMOS technology.With the reduction of process size,the time resolution is greatly improved.In order to build the link between voltage signals and timepluse,two novel voltage to delay circuits with high linearity and rail to rail input dynamic range are implemented by combining current starving technology and body biasing technology,which effectively solves the problem that traditional structures have to compromise between linearity and input dynamic range.(3)Using XFAB 0.18μm standard CMOS process,a VCO type one-step conversion time domain ADC is implemented in Cadence virtuoso.When the input frequency is42578.125 Hz and 100 k S/S sampling rate,the results show that the SFDR,SNDR and ENOB of the ADC are improved from 38.9501 dB to 70.6534 dB,37.9755 dB to 67.2136 dB,6.0159-bits to 10.8727-bits.Comparing the simulation results of the ADC with different linearity delay cells,the SFDR,SNDR and ENOB of the ADC are improved by23.3dB,13.5dB and 2.2-bits in 150 k S/S sampling rate respectively. |
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