Research And Design Of High-Precision SAR ADC Based On Low-Noise VCO Comparator

With the rapid development of various information technologies,the hardware sys-tem on which it depends is becoming more and more important.Analog-to-Digital Con-verter(ADC)acts as a bridge between the analog world and digital circuits in the hardware circuit system.In the fields of artificial intelligence,industrial automation and control,5G communication systems and biomedical systems,as well as some consumer electronic products,the requirements for the quantification accuracy and conversion speed of ADCs are getting higher and higher.Therefore,it has very important research significance in the two directions of improving accuracy and speed.Successive Approximation Register ADC has the characteristics of high digitization of the circuit structure and low design complexity.Its power consumption and area benefit from the shrinking process size and are continuously reduced and optimized.It has a higher figure of merit,widely used in a variety of high-precision,medium-high speed scenes.In this paper,the key technology of high-precision low-power SAR ADC is studied,and a 13-bit 64k S/s SAR ADC is designed.This ADC chip is mainly aimed at wearable devices,such as biomedical systems such as bracelets and ECG monitoring.The ADC de-signed in this paper adopts a comparator structure based on a voltage-controlled oscillator to obtain a comparator performance with a higher figure of merit.For metastability,a de-tection method based on the number of time-domain VCO oscillations is proposed.This paper presents a residue oversampling technique based on the rotation of the capacitor slices for capacitance mismatch.After modeling and verification,the static performance and dynamic performance of the ADC have a considerable improvement without the need for additional foreground or background capacitance correction technology.Thanks to this calibration-free strategy to reduce the impact of mismatch and noise,the original de-sign uses a 180nm CMOS process to obtain an effective number of 12.81 bits under low-frequency input.The SNDR and SFDR are 78.88dB and 90.67dB,achieving the Fo M_sand Fo M_wof 174dB and 21.5f J/conv.-step,respectively.Under the Nyquist frequency input,the effective number of bits is 12.76,and the SNDR and SFDR are 78.58dB and90.69dB,respectively.Due to the area and power consumption advantages of the residual oversampling technology,the core area of the chip is 0.2mm~2,and the power consumption is 9.885μW.