Improvement Of Process Window And Reliability Of Super Junction Devices

Superjunction MOSFET（SJ-MOSFET）breaks the"Silicon Limit"by introducing a2D-dimensional electric field（E-field）.However,the distribution of the 2D-dimensional E-field is deeply affected by the degree of charge balance in the columns,and the existence of process-errors can easily lead to the appearance of the charge imbalance（CIB）,which can seriously affect the breakdown voltage（BV）and reliability of the SJ-MOSFET.With the development of SJ technology in the direction of larger aspect ratios,this effect will become more serious with the increase of manufacturing difficulty.Therefore,it is meaningful to study the improvement of robustness of the BV and reliability relative to the CIB for SJ-MOSFET.In this article,the process-window of BV(W_BV)is defined to describe the impact of CIB on the BV of SJ-MOSFET,and the maximum dynamic avalanche current(I_as)that the device can tolerate during the unclamping inductive switching（UIS）is used to characterize the reliability of the device.Thus,the reaearch to improve the robustness of W_BV and I_as to CIB in SJ-MOSFET is carried out.The main work of this article is as follows:1.The basic structure,mechanism of withstand voltage and working mode of SJ-MOSFET are explained in this article.And several manufacturing methods of SJ structure and their advantages and disadvantages are introduced.In addition,this article also explains the testing principles,the failure mechanisms and the failure judgment methods of UIS testing.2.The article defines the parameter K_CIB=Q_P/Q_N to characterize the degree of CIB of columns,explains that the tilt of E-field under CIB is the cause of the sharp drop in the BV of the SJ-MOSFET,and points out that enhancing the middle E-field and reducing the E-field at the top and the bottom of the SJ can effectively increase W_BV.Then,the charge superposition model of the gradually doped superjunction in the column is established in this paper,using a and b as the concentration change parameters of P-column and N-column,respectively.By decomposing the internal charges,the electric field distribution changes under different gradually doped columns can be predicted and analyzed.Based on the analysis of the charge superposition model,it is proposed that the W_BV can be increased by adopting gradually-doped column with negative（a>0）and positive（b<0）gradients of P-column and N-column,respectively.In the sinulation,the impurity change parameters a and b of the P-column and N-column are selected as 0.2 and-0.2,respectively.And the results show that the W_BV can be increased by 44.44%,while BV_maxis only slightly reduced by 5.578%,thus verifying the above conclusion.3.The changes of I_as caused by the different values of K_CIB are analyzed.The influence of thermal resistance(R_th)and Pbody doping concentration on I_as is discussed.The results show that increase of R_th will make I_as decrease rapidly,while the Pbody concentration only affects I_as when K_CIB is very small.This article further analyzes the change of I_as for SJ-MOSFET in the range of K_CIB from 0.5 to 1.5.It is found that I_as will experience three stages:rising,slowing down of rising rate and falling.And the cause of UIS test failure will also change from being mainly affected by the parasitic transistor to being affected by temperature.It is pointed out that the optimization of the I_as curve needs to reduce the current concentration at the upper and lower ends when the value of K_CIB is too small or too large.Since the current depends on the change of the E-field,it again studied the influence of the graded column on I_as,and found that the doping of a<0 or b<0 can also optimize the I_as of the device.4.The multi-step epitaxy and ion implantation process flow of SJ-MOSFET is designed,and the actual test results verify that the optimized doping method can effectively increase the W_BV and enhance the reliability of the device.