Research On The Technology Of High-speed Serial Interface Receiver Equalizer

With the development of microelectronics,the speed of high-speed Ser Des is getting higher and higher.The high frequency attenuation of the channel to the signal also increases with the increase of the rate.The receiver of the Ser Des needs to compensate the high frequency gain of the signal output from the channel to reduce the inter-code interference between the transmitted signals.The digital equalizer is more complex to realize.The analog equalizer has the characteristics of simple structure and small power consumption.In recent years,the mainstream equalizer is the combination of the analog equalizer and the digital equalizer.The paper analyzes the channel characteristics firstly,and the actual channel based on S parameter(Scattering parameters in microwave networks)is simulated to determine its frequency domain response and time domain impulse response.Then,on the basis of introducing the common Equalizer,this paper focuses on the theoretical analysis,formula derivation and circuit simulation of the typical analog Equalizer--Continuous Time Linear Equalizer(CTLE),so as to guide the circuit design.Then,an analog front-end for 4-level Pulse Amplitude Modulation(PAM4)working on a40 Gbps receiver is designed using TSMC65 nm CMOS process.The front end consists of a CTLE,a Variable Gain Amplifier(VGA)and a Buffer.The CTLE gain at 10 GHz is adjustable at 16 levels from 6.42 d B to 12.46 d B by using degenerated capacitance and inductance peaking technology.The equivalent transconductance is controlled by parallel current in VGA,and the low-frequency gain is adjustable at 16 levels from-4.58 d B to 5.75 d B.Buffer adopts Ctle spread spectrum technology,-3d B bandwidth reaches 20 GHz,and the analog front end provides 11.37 d B gain compensation at10 GHz after a 40Gb/s PAM4 signal is attenuated through a 17.13 d B channel.The analog front end provides 6.9d B gain compensation at 10 GHz after signal attenuation through the 6.39 d B channel.The equalization range of the whole circuit is 6.35 d B to12.46 d B at 10 GHz,and the power consumption is 15.1m W.Finally,a multifrequency adjustable CTLE is designed,which solves the shortcoming of non-adjustable low frequency of CTLE in the analog front end.