56Gb/s PAM4 SerDes Transmitter Design Based On 65nm CMOS Process

With the continuous development of 5G communication system,IOT and Big Data,people have greater and greater requirements for data transmission rate.In the next generation 400 G Ethernet,the single channel data rate requirement has reached more than 50Gb/s,the traditional serial transmission system based on NRZ signal can not meet the system requirements.The Fourth-order Pulse Amplitude Modulation(PAM4)signal has four levels,each level contains two bits of information.The bandwidth occupied by PAM4 signal is only half of that occupied by NRZ signal at the same rate,which has been widely used in ultra-high speed serial transmission system.The PAM4 transmitter designed in this thesis is mainly composed of feedforward equalizer(FFE)and Driver.FFE adopts half rate structure,which mainly includes delay unit,multiplexer and multiplier-adder.The delay unit adopts the digital delay unit structure composed of D flip-flop and latch.The multiplexer is the module with the highest working speed in this design.The multiplexer adopts the current mode structure.The multiplier-adder includes three taps.The tap coefficient is controlled by adjusting the gate voltage of the tail current source.In order to reduce the design difficulty of the clock circuit,the integer digital element interval delay is adopted between the tap coefficients.The Driver also needs to work at high speed,and also adopts current mode structure.The PAM4 transmitter in this thesis also includes the clock circuit required by FFE,which is provided by phase-locked loop(PLL).Among them,PLL adopts charge pump phase-locked loop(CPPLL)structure,which mainly includes frequency and phase discriminator(PFD),charge pump(CP),low-pass filter(LPF),voltage controlled oscillator(VCO)and frequency divider(DIV).The charge pump adopts cascode source switch structure to reduce the non-ideal characteristics of the switch.The VCO adopts LC structure to obtain good phase noise characteristics.The DIV adopts four divide-by-2 circuits,which is one-stage current mode frequency divider and three-stage TSPC frequency divider respectively,so as to realize the compromise between power consumption and speed.This thesis completes the layout design and post simulation of the whole transmitter.The layout area including pad is 758μm×505μm.The power consumption under 1.2V power supply voltage is 336 m W.The post simulation results show that when passing through a channel with attenuation of-7.56 d B at 14 GHz,the horizontal opening of the signal eye diagram behind the equalizer reaches 0.504 UI and the vertical opening reaches 160 m Vpp.The phase noise of VCO at 1MHz is-107 d Bc/Hz and the overall RMS jitter is396 fs.The post simulation results show that the designed circuit meets the index requirements.With the explosive growth of data transmission rate,the PAM4 SerDes transmitter with a rate of56Gb/s studied in this thesis has certain theoretical significance and application value for the design and implementation of high-speed PAM4 transmitter.