Research And Implementation Of Spiking Neural Networks Accelerator Based On FPGA

The human brain has a high level of intelligence and low power consumption,so its computing mode is very worth studying.Brain-like computing realizes information processing by imitating the operating mechanism of the biological brain.It is mainly based on Spiking Neural Networks(SNN),and its implementation methods are mainly divided into hardware implementation and software implementation.The hardware implementation method generally uses specialized brain-like computing chips and systems to implement spiking neural networks.This method can provide better energy efficiency indicators,but it is costly and has poor adaptability.When it does not match the application load,the calculated energy efficiency performance is often greatly reduced.The software implementation method is to perform functional simulation by designing a brain-like simulator.At present,the more mature simulators have complete functions and a complete application ecology.They have the advantages of strong calculation flexibility and high accuracy.However,due to the high computational complexity,there are problems such as slow simulation speed and high power consumption.If the two implementation methods are combined,through the software and hardware co-design,the hardware circuit design of the simulator performance bottleneck or computationally intensive points can be achieved while ensuring a good application ecology while achieving higher computational energy efficiency.This paper proposes a high energy efficiency implementation of the NEST brain-like simulator based on the FPGA heterogeneous platform PYNQ cluster.The main work of this paper is as follows:First,select a suitable brain-like simulator and analyze its performance.Firstly,the performance of several mature brain-like simulators is compared,and the NEST simulator is selected as the research object of the brain-like architecture based on performance evaluation indicators such as simulation range and calculation time.Later,this paper analyzes the code of the NEST simulator,sorts out its work flow,and models the load characteristics of the NEST simulator through performance indicators such as memory consumption,calculation time,and communication time,and speculates on the performance bottleneck and computational intensive points of the simulator.Provide theoretical basis for the subsequent design of FPGA hardware circuit accelerator for NEST simulator.Second,realize the NEST simulator based on FPGA heterogeneous computing platform.Realize the IAF neuron update hardware circuit through the FPGA parallel and pipeline design method.Design software and hardware data interaction interface,optimize memory allocation,reduce the total amount of data transmission and other methods to achieve and optimize the data transmission between ARM and FPGA,and increase the computing parallelism through data fixed-point quantization method.Through actual tests,the calculation speed of the NEST simulator implemented by the FPGA heterogeneous computing platform is at least 6.3 times higher than that of the ARM Cortex-A9 computing platform without acceleration,and the energy efficiency ratio is at least 7 times higher.Third,to achieve a large-scale NEST brain-like computing cluster with scalable scale and adjustable computing power.Build NEST computing cluster through Ethernet and MPI communication mechanism.Optimize cluster file management through the network file system,design an automatic load mapping mechanism,realize the preliminary analysis of the calculation model,calculate the number of nodes with the best performance and the minimum number of nodes in the cluster,and improve the efficiency of cluster usage.The experimental results show that: for different computing models,when the cluster runs with the optimal number of nodes,the computing performance of the neuron update part of the cluster is improved by more than 4.6 times compared with AMD 3600 X,and at least 7.5 times higher than that of Intel Xeon E5-2620v2;the energy efficiency of the update is more than 5.3 times higher than that of AMD 3600 X and 7.9 times higher than that of Intel Xeon E5-2620v2.