Research And Design Of High Performance Δ~2Σ ADC For Wearable EEG Signal Measurement

As a hot spot in today’s society,wearable medical devices can easily collect human health data,predict and diagnose diseases early.First of all,it is necessary to accurately collect various bioelectric signals.The bioelectric signal represented by EEG has small amplitude and low frequency,and is susceptible to interference from low-frequency noise,electrode imbalance,and motion artifacts.This requires the biosignal acquisition front-end to have high accuracy,common-mode rejection ratio and sufficient electrode offset suppression capability.Compared with the traditional"IA+ADC"structure,theΔ²Σ ADC can achieve high-precision direct digital conversion without pre-amplification,and can suppress the DC offset of the electrode.So it has unique advantages in the field of bioelectric signal measurement.In this thesis,combined with the characteristics and measurement requirements of EEG signals,a high-performance bioelectric signal measurement circuit is proposed based on theΔ²Σ ADC structure.The EEG signal measurement circuit designed in the thesis adopts the second-orderΔ²Σ ADC structure,and the parameter and time sequence design are optimaized according to signals of each node to ensure the correct and reliable operation of the system.The integrators adopt the Hybrid structure to avoid the usage of anti-aliasing filter.As a key module,the capacitive coupling instrumentation amplifier combines chopper modulation,current multiplexing,switched capacitor common mode feedback,dual dead zone switching and other techniques to optimize noise,power consumption and linearity.The system uses CDAC reusing method to reduce circuit area and circuit complexity,while using DWA technique to suppress the capacitor mismatch noise of CDAC.In order to meet the requirements of time sequence and op-amp output range,the system selects a 5bit asynchronous clock SAR ADC as the quantizer,and its reference voltage is set to VDD/8,which achieves an 8 times quantization gain and avoids the usage of additional gain stage.The circuit and layout design of the chip has been completed under the UMC 55nm CMOS process.The simulation results show that the chip consumes 33.79μA at 1.2V voltage supply,and the input refered noise is 0.182μV_RMS.The dynamic range of the system reaches 106d B,and the peak signal-to-noise ratio is 111.3d B.The common-mode rejection ratio at 60Hz is 111.8d B.The system can tolerate electrode offsets as high as±150m V theoretically,and can stabilize quickly within 0.03ms when a100m V step signal happens,while the quantizer output does not contain any DC offset signals.