Study On Evaluation And Improvement On Packaging Performance Of Multi-chip SiC IGBT Device

Multi-chip Silicon Carbide(SiC)Insulated Gate Bipolar Transistor(IGBT)devices have the advantages of high breakdown field,and low on-resistance,which are the ideal devices for high-voltage,large-capacity power electronic equipments.However,due to the difference in chip layout and connection,uneven distribution of electrical-thermal-mechanical parameters in multi-chip devices is prone to occur,and the large Young’s modulus of SiC is likely to cause the early failure of the weakest part.The existing modeling and analysis methods for single-chip device are difficult to accurately and comprehensively evaluate the reliability of the multi-chip device.It is of practical significance to carry out research on performance evaluation and improvement of multi-chip SiC devices.The thesis is based on the sub-project of the National Key Research and Development Program.To evaluate and improve the packaging performance of multi-chip SiC IGBT device,the thesis conducts research from multi-physics modeling,power cycling simulations and reliability evaluation of SiC IGBT,multi-chip current sharing characteristics analysis,and packaging reliability improvement design.The main contents of the thesis include:(1)Aiming at the thermal-mechanical parameters of multi-chip SiC IGBT device packaging materials affected by temperature,the multi-physics model of the device considering the dependence of temperature is proposed to obtain the electric-thermal-force distribution of multi-chip devices.First,the packaging of the multi-chip SiC IGBT device is introduced.Secondly,the multi-physics model is established based on the measured output characteristic curve of SiC IGBT and the temperature dependent parameters of packaging materials.Finally,calculation results are extracted to evaluate the electro-thermal-mechanical performance of the device.(2)Considering that the complicated internal coupling relationship of multi-chip SiC IGBT devices will lead to the difficulty in the weakest part location and reliability evaluation,power cycling simulations are conducted and reliability assessment based on failure physical models are proposed.Firstly,the multi-physics model of the multi-chip SiC IGBT device is simplified.Secondly,power cycling simulations under different conditions are carried out to calculate the strain of solder layer and bond wire.Physical lifetime models are used to evaluate the life of the SiC IGBT device packaging.Finally,the analytical lifetime model is adopted to fit the lifetime calculation results to provide a theoretical basis for experiment conditions.(3)Aiming at the differences in chip layout,connection and temperature distribution affect the current distribution of multi-chip SiC devices,the current sharing characteristics of the device are studied.Firstly,the packaging parasitic parameters are extracted.Secondly,the circuit model of the multi-chip device is established.The influence of the gate resistance on the switching behaviors is studied.The dynamic current distribution inside device is obtained.Finally,the influence of bond wire failure on parasitic inductance and uneven temperature distribution are investigated.The switching waveforms of multi-chip devices under failure conditions are obtained.(4)Aiming at the uneven parameter distribution,low reliability,high inductance of multi-chip SiC devices,a press pack SiC device packaging based on the symmetrical layout and the principle of inductance cancellation is designed.First,the device packaging are proposed,and the multi-physics model is established.Secondly,the impact of packaging materials on the thermal-mechanical performance is studied.Response surface method is proposed to optimize the packaging parameters to achieve the best device performance.Then,power cycling simulations are carried out to evaluate the reliability.Finally,the parasitic inductance is extracted and the device circuit model is established.The results are compared with the previous packaging.The results of the thesis can provide technical support for comprehensive evaluation of the packaging performance of multi-chip SiC devices and theoretical guidance for reliability test experiments of multi-chip SiC devices,which also lay the foundation for the reliability optimization design of multi-chip SiC device packaging.